Memory refresh operation with page open

• US 9,659,626 B1
• Filed: 12/26/2015
• Issued: 05/23/2017
• Est. Priority Date: 12/26/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bains, Kuljit S., Querbach, Bruce, Halbert, John B.
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US14/998,091
• Time in Patent Office: 514 Days
• Field of Search: 365203
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

Claims

1. A memory device comprising:

a memory array including a plurality of memory banks; and

a control logic to provide control operations for the memory device including a page open refresh mode;

wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including;

precharge of one or more memory banks of the plurality of memory banks,

refresh of the one or more memory banks, and

activation of the memory page.

2. The memory device of claim 1, further comprising a mode register set including a mode register to store an indication to enable or disable the page open refresh mode.

3. The memory device of claim 2, wherein the mode register for page open refresh mode is set in response to a received write command.

4. The memory device of claim 1, wherein the refresh command is one of a refresh command for all memory banks of the memory device or a refresh command for a specific memory bank of the memory device.

5. The memory device of claim 1, wherein the control logic is operable to perform the refresh cycle without receipt of a precharge command or an activate command.

6. The memory device of claim 1, wherein the memory device comprises a dynamic random access memory (DRAM) device.

7. The memory device of claim 6, wherein the DRAM device comprises a double data rate (DDR) synchronous DRAM (SDRAM) memory device.