SRAM with stacked bit cells

• US 9,659,632 B2
• Filed: 10/20/2015
• Issued: 05/23/2017
• Est. Priority Date: 10/20/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Diaz, Carlos H., Colinge, Jean-Pierre, Wang, Chih-Hao, Guo, Ta-Pen
• Primary Examiner(s): King, Douglas
• Application Number:
  US14/918,068
• Publication Number:
  US 20170110180A1
• Time in Patent Office: 581 Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.

Claims

1. A static random access memory (SRAM), comprising:

a plurality of bit cells, each comprising;

a first inverter, comprising a first pull-up transistor and a first pull-down transistor;

a second inverter cross-coupled with the first inverter, comprising a second pull-up transistor and a second pull-down transistor;

a first pass gate transistor coupled between an input of the first inverter and a bit line; and

a second pass gate transistor coupled between an input of the second inverter and a complementary bit line,

wherein the plurality of bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each one of the plurality of bottom tier cells is disposed under a corresponding one of the plurality of top tier cells,

wherein the first inverter of each one of the top tier cells is disposed over the second inverter of a corresponding bottom tier cell, and the second inverter of the top tier cell is disposed over the first inverter of the corresponding bottom tier cell; and

wherein drains of the transistors of each top tier cell of the plurality of top tier cells are disposed on a first layer of the substrate, gates of the transistors of the top tier cell are disposed on a second layer under the first layer of the substrate, sources of the transistors of the top tier cell and sources of the transistors of the corresponding bottom tier cell are disposed on a third layer under the second layer of the substrate, gates of the transistors of the corresponding bottom tier cell are disposed on a fourth layer under the third layer of the substrate, and drains of the transistors of the corresponding bottom tier cell are disposed on a fifth layer under the fourth layer of the substrate.

2. The SRAM as claimed in claim 1, wherein the first pass gate transistors of the plurality of top tier cells and the corresponding plurality of bottom tier cells are coupled to a same bit line, and the second pass gate transistors of the top tier cell and the corresponding bottom tier cell are coupled to a same complementary bit line.

3. The SRAM as claimed in claim 1, wherein the drain of the second pass gate transistor of the top tier cell is coupled to the gates of the second pull-up transistor and the second pull-down transistor of the top tier cell via a first metal on drain (MD) contact between a metal layer on the substrate and the first layer, and a first metal on poly (MP) contact between the metal layer and the second layer, wherein the drain of the second pass gate transistor of the corresponding bottom tier cell is coupled to the drains of the first pull-up transistor and the first pull-down transistor of the corresponding bottom tier cell via a drain pad of the fifth layer, wherein the sources of the second pass gate transistors of the top tier cell and the corresponding bottom tier cell are coupled to a source pad of the third layer, and the complementary bit line is coupled to the source pad of the third layer from the metal layer via a first via and a second MD contact between the metal layer and the third layer of the substrate.

4. The SRAM as claimed in claim 3, wherein a first word line is coupled to the gate of the second pass gate transistor of the top tier cell from the metal layer via a second via and a second MP contact between the metal layer and the second layer of the substrate, and a second word line is coupled to the gate of the second pass gate transistor of the corresponding bottom tier cell from the metal layer via a third via and a third MP contact between the metal layer and the fourth layer of the substrate.

5. The SRAM as claimed in claim 1, wherein the first pull-up transistor is adjacent to the second pull-up transistor in the top tier cell, wherein the first pull-up transistor of the top tier cell is disposed over the second pull-up transistor of the corresponding bottom tier cell, and the second pull-up transistor of the top tier cell is disposed over the first pull-up transistor of the corresponding bottom tier cell, wherein the sources of the first and second pull-up transistors of the top tier cell and the corresponding bottom tier cell are coupled to a source pad of the third layer, and a power line is coupled to the source pad of the third layer from the metal layer via a via and a metal on drain (MD) contact between the metal layer and the third layer of the substrate.

6. The SRAM as claimed in claim 1, wherein the first pull-down transistor is adjacent to the second pull-down transistor in the top tier cell, wherein the first pull-down transistor of the top tier cell is disposed over the second pull-down transistor of the corresponding bottom tier cell, and the second pull-down transistor of the top tier cell is disposed over the first pull-down transistor of the corresponding bottom tier cell, wherein the sources of the first and second pull-down transistors of the top tier cell and the corresponding bottom tier cell are coupled to a source pad of the third layer, and a ground line is coupled to the source pad of the third layer from the metal layer via a via and a metal on drain (MD) contact between the metal layer and the third layer of the substrate.

7. The SRAM as claimed in claim 1, wherein the drain of the first pass gate transistor of the top tier cell is coupled to the gates of the first pull-up transistor and the first pull-down transistor of the top tier cell via a first metal on drain (MD) contact between a metal layer on the substrate and the first layer, and a first metal on poly (MP) contact between the metal layer and the second layer, wherein the drain of the first pass gate transistor of the corresponding bottom tier cell is coupled to the drains of the second pull-up transistor and the second pull-down transistor of the corresponding bottom tier cell via a drain pad of the fifth layer, wherein the sources of the first pass gate transistors of the top tier cell and the corresponding bottom tier cell are coupled to a source pad of the third layer, and the bit line is coupled to the source pad of the third layer from the metal layer via a first via and a second MD contact between the metal layer and the third layer of the substrate.

8. The SRAM as claimed in claim 7, wherein a first word line is coupled to the gate of the first pass gate transistor of the top tier cell from the metal layer via a second via and a second MP contact between the metal layer and the second layer, and a second word line is coupled to the gate of the first pass gate transistor of the top tier cell from the metal layer via a third via and a third MP contact between the metal layer and the fourth layer of the substrate.

9. The SRAM as claimed in claim 1, wherein the first pull-down transistor is adjacent to the second pull-down transistor in the top tier cell, wherein the first pull-down transistor of the top tier cell is disposed over the second pull-down transistor of the bottom tier cell, and the second pull-down transistor of the top tier cell is disposed over the first pull-down transistor of the bottom tier cell, wherein the sources of the first and second pull-down transistors of the top tier cell and the bottom tier cell are coupled to a source pad of the third layer, and a ground line is coupled to the source pad of the third layer from the metal layer via a via and a MD contact between the metal layer and the third layer of the substrate.

10. The SRAM as claimed in claim 1, wherein the drain of the first pass gate transistor of the top tier cell is coupled to the gates of the first pull-up transistor and the first pull-down transistor of the top tier cell via a first metal on drain (MD) contact between a metal layer and the first layer, and a first metal on poly (MP) contact between the metal layer and the second layer, wherein the drain of the first pass gate transistor of the bottom tier cell is coupled to the drains of the second pull-up transistor and the second pull-down transistor of the bottom tier cell via a drain pad of the fifth layer, wherein the sources of the first pass gate transistors of the top tier cell and the bottom tier cell are coupled to a source pad of the third layer, and the bit line is coupled to the source pad of the third layer from the metal layer via a via and a second MD contact between the metal layer and the third layer of the substrate.

11. A static random access memory (SRAM), comprising:

a plurality of bit cells, each comprising;

a first inverter, comprising a first pull-up transistor and a first pull-down transistor;

a second inverter cross-coupled with the first inverter, comprising a second pull-up transistor and a second pull-down transistor;

a first pass gate transistor coupled between an input of the first inverter and a bit line; and

a second pass gate transistor coupled between an input of the second inverter and a complementary bit line,

wherein the bit cells are divided into a plurality of top tier cells formed in a first array and a corresponding plurality of bottom tier cells formed in a second array disposed under the first array,

wherein the first pass gate transistor, the second pull-up transistor, and the second pull-down transistor of the top tier cell are disposed in a first column of the first array, and the second pass gate transistor, the first pull-up transistor, and the first pull-down transistor of the corresponding bottom tier cell are disposed in a second column of the second array parallel to and under the first column,

wherein sources of the transistors of the top tier cell and sources of the transistors of the corresponding bottom tier cell are disposed between the first and second columns,

wherein each top tier cell and corresponding bottom tier cell are coupled to a same bit line and different word lines.

12. The SRAM as claimed in claim 11, wherein the second pass gate transistor, the first pull-up transistor, and the first pull-down transistor of the top tier cell are disposed in a third column of the first array parallel and adjacent to the first column of the first array, and the first pass gate transistor, the second pull-up transistor, and the second pull-down transistor of the corresponding bottom tier cell are disposed in a fourth column of the second array parallel to and under the third column of the first array, wherein the fourth column is parallel and adjacent to the second column in the second array.

13. The SRAM as claimed in claim 11, wherein the second pass gate transistor of the top tier cell is disposed on a first row of the first array, and the second pass gate transistor of the corresponding bottom tier cell is disposed on a second row of the second array parallel to and under the first row of the first array.

14. The SRAM as claimed in claim 13, wherein the first and second pull-up transistors of the top tier cell are disposed on a third row of the first array, and the first and second pull-up transistors of the corresponding bottom tier cell are disposed on a fourth row of the second array parallel to and under the third row of the first array, wherein the third row is parallel and adjacent to the first row in the first array.

15. The SRAM as claimed in claim 14, wherein the first and second pull-down transistors of the top tier cell are disposed on a fifth row of the first array, and the first and second pull-down transistors of the corresponding bottom tier cell are disposed on a sixth row of the second array parallel to and under the fifth row of the first array, wherein the fifth row is parallel and adjacent to the third row in the first array.

16. The SRAM as claimed in claim 15, wherein the first pass gate transistor of the top tier cell is disposed on a seventh row of the first array, and the first pass gate transistor of the corresponding bottom tier cell is disposed on an eighth row of the second array parallel to and under the seventh row of the first array, wherein the seventh row is parallel and adjacent to the fifth row in the first array.

17. A static random access memory (SRAM), comprising:

a top tier bit cell coupled to a first word line, a bit line, and a complementary bit line of a metal layer, comprising six transistors in a substrate, wherein drains of the transistors of the top tier cell are disposed on a first layer of the substrate, gates of the transistors of the top tier cell are disposed on a second layer under the first layer of the substrate, and sources of the transistors of the top tier cell are disposed on a third layer under the second layer of the substrate; and

a bottom tier bit cell disposed under the top bit cell and coupled to a second word line, the bit line, and the complementary bit line of the metal layer, comprising six transistors in the substrate, wherein sources of the transistors of the bottom tier cell are disposed on the third layer, gates of the transistors of the bottom tier cell are disposed on a fourth layer under the third layer of the substrate, and drains of the transistors of the bottom tier cell are disposed on a fifth layer under the fourth layer of the substrate,

wherein the six transistors of the top tier bit cell and the bottom tier bit cell respectively comprise;

a first pull-up transistor and a first pull-down transistor, wherein a first inverter is formed by the first pull-up and pull-down transistors;

a second pull-up transistor and a second pull-down transistor, wherein a second inverter cross-coupled with the first inverter is formed by the second pull-up and pull-down transistors;

a first pass gate transistor coupled between an input of the first inverter and the bit line; and

a second pass gate transistor coupled between an input of the second inverter and the complementary bit line,

wherein the first and second pass gate transistors of the top tier bit cell are controlled by the first word line, and the first and second pass gate transistors of the bottom tier bit cell are controlled by the second word line.

18. The SRAM as claimed in claim 17, wherein the drain of the second pass gate transistor of the top tier cell is coupled to the gates of the second pull-up transistor and the second pull-down transistor of the top tier cell via a first metal on drain (MD) contact between the metal layer and the first layer, and a first metal on poly (MP) contact between the metal layer and the second layer, wherein the drain of the second pass gate transistor of the bottom tier cell is coupled to the drains of the first pull-up transistor and the first pull-down transistor of the bottom tier cell via a drain pad of the fifth layer, wherein the sources of the second pass gate transistors of the top tier cell and the bottom tier cell are coupled to a source pad of the third layer, and the complementary bit line is coupled to the source pad of the third layer from the metal layer via a first via and a second MD contact between the metal layer and the third layer of the substrate.

19. The SRAM as claimed in claim 17, wherein the first pull-up transistor is adjacent to the second pull-up transistor in the top tier cell, wherein the first pull-up transistor of the top tier cell is disposed over the second pull-up transistor of the bottom tier cell, and the second pull-up transistor of the top tier cell is disposed over the first pull-up transistor of the bottom tier cell, wherein the sources of the first and second pull-up transistors of the top tier cell and the bottom tier cell are coupled to a source pad of the third layer, and a power line is coupled to the source pad of the third layer from the metal layer via a via and a metal on drain (MD) contact between the metal layer and the third layer of the substrate.

20. The SRAM as claimed in claim 17, wherein the top tier bit cell is dual-ported.