Via stack fault detection

• US 9,659,668 B2
• Filed: 05/30/2014
• Issued: 05/23/2017
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Veches, Anthony D
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): RAJAPUTRA, SURESH KS
• Application Number:
  US14/291,589
• Publication Number:
  US 20150348647A1
• Time in Patent Office: 1,089 Days
• Field of Search: None
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators

Abstract

A method and apparatus are disclosed. One such method includes selecting a die of a plurality of dies that are coupled together through a via stack. A via on the selected die can be coupled to ground. A supply voltage is coupled to an end of the via stack and a resulting current measured. A calculated resistance is compared to an expected resistance to determine if a fault exists in the via stack.

Claims

1. An apparatus for fault detection in a via stack, the apparatus comprising:

a plurality of dies coupled together through the via stack, each die having a reference voltage selection circuit coupled to a respective via, each die further having a circuit configured to select its respective die and enable the reference voltage selection circuit to couple a reference voltage to the respective via; and

a connection to the via stack configured to apply a supply voltage to the via stack and measure a resulting current through the via stack.

2. The apparatus of claim 1, wherein the reference voltage is circuit ground.

3. The apparatus of claim 1, wherein the via is a through-silicon via (TSV).

4. The apparatus of claim 1, wherein the circuit comprises a receiver configured to control coupling of the reference voltage to the respective via, the circuit including the reference voltage selection circuit and receiver circuitry coupled between the respective via and circuitry of the respective die.

5. The apparatus of claim 1, wherein the reference voltage selection circuit comprises a transistor that is configured to be turned on by an active enable signal to connect the respective via to ground.

6. The apparatus of claim 5, wherein only a subset of the plurality of dies is configured to include the resulting current in response to which die is selected, the subset including a quantity of dies that is less than the plurality of dies.

7. The apparatus of claim 6, wherein the subset of the plurality of dies includes one or more dies between a die that originates the supply voltage and the selected die.

8. The apparatus of claim 1, wherein the plurality of dies are stacked vertically.

9. An apparatus for via stack fault detection, the apparatus comprising:

a plurality of dies;

a plurality of die-to-die interconnects, each die-to-die interconnect coupling a pair of adjacent dies of the plurality of dies;

a respective die via, on each of the plurality of dies, wherein the respective die via is switchably coupled to ground, each respective die via coupled to adjacent die vias through adjacent die-to-die interconnects to form the via stack;

a supply voltage connection switchably coupled to one end of the via stack and configured to apply a supply voltage to the via stack;

a connection to the via stack configured to measure a resulting current through the via stack.

10. The apparatus of claim 9, wherein the die via is switchably coupled to ground through a transistor in a die receiver.

11. The apparatus of claim 10, wherein the die receiver further comprises buffers, amplifiers, and logic between the respective die via and circuitry of a respective die.

12. The apparatus of claim 10, further comprising a die identification circuit configured to generate an enable signal for the transistor in response to an active chip select signal.

13. The apparatus of claim 10, further comprising a die identification circuit configured to generate an enable signal for the transistor in response to receiving a valid address.

14. The apparatus of claim 9, further comprising a circuit configured to enable a transistor to couple the respective die via to ground in response to an active chip select signal and an active transistor control gate signal.

15. The apparatus of claim 9, wherein the supply voltage connection is an external connection to the via stack.

16. The apparatus of claim 9, wherein the supply voltage connection is an internal connection to the via stack.

17. The apparatus of claim 16, wherein the internal connection comprises a receiver circuit having a supply voltage enable circuit that switchably couples the supply voltage to the via stack.

18. A method for fault detection of a via stack, the method comprising:

selecting a die of a plurality of dies;

coupling a via of the selected die to circuit ground to create one end of the via stack;

applying a supply voltage to an opposite end of the via stack; and

measuring a resulting current on the via stack.

19. The method of claim 18, further comprising determining if a fault exists in the via stack in response to a comparison of the measured current to an expected current.

20. The method of claim 18, further comprising:

calculating a resistance of the via stack; and

determining if a fault exists in the via stack in response to a comparison of the calculated resistance to an expected resistance.

21. The method of claim 20, further comprising detecting a fault in the via stack when the calculated resistance is not equal to the expected resistance.

22. The method of claim 21, further comprising:

detecting a short in the via stack when the calculated resistance is less than the expected resistance; and

detecting an open connection when the calculated resistance is greater than the expected resistance.

23. The method of claim 18, wherein selecting the die of the plurality of dies comprises selecting a subset of the plurality of dies.

24. The method of claim 23, wherein selecting the subset of the plurality of dies comprises selecting the dies under test, and repeating the method for via stack fault detection after selecting a subset of the dies under test.

25. The method of claim 18, including selectively isolating circuitry of the selected die from the via of the selected die using receiver circuitry.