Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer

• US 9,659,670 B2
• Filed: 07/28/2009
• Issued: 05/23/2017
• Est. Priority Date: 07/28/2008
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Choi, SunYong, Pae, YeonHo, Chang, Ellis
• Primary Examiner(s): HUANG, FRANK F
• Application Number:
  US13/056,623
• Publication Number:
  US 20110187848A1
• Time in Patent Office: 2,856 Days
• Field of Search: 348 92
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer are provided.

Claims

1. A computer-implemented method for classifying defects detected in a memory device area on a wafer, comprising:

using a computer system to perform the following steps;

determining positions of inspection data acquired for the memory device area by an inspection system, wherein the memory device area comprises different types of blocks, and wherein the inspection data comprises data for defects detected in the memory device area;

determining positions of the defects with respect to a predetermined location within the blocks in which the defects are located based on the positions of the inspection data; and

classifying the defects based on the positions of the defects within the blocks, wherein said classifying comprises determining a ratio of the numbers of the defects detected in at least two of the different types of blocks and classifying the defects in the at least two of the different types of blocks based on the ratio.

2. The method of claim 1, wherein the predetermined location comprises a center or a corner of the blocks.

3. The method of claim 1, further comprising reporting x, y addresses of the different types of blocks within the memory device area and the positions of the defects within the blocks, wherein the positions of the defects within the blocks comprise x, y locations with respect to the predetermined location within the blocks.

4. The method of claim 1, wherein said classifying further comprises classifying the defects based on the positions of the defects within the blocks and the types of the blocks in which the defects are located.

5. The method of claim 1, wherein said classifying further comprises determining if the defects are systematic defects.

6. The method of claim 1, wherein said classifying further comprises stacking the inspection data for multiple blocks having the same type to separate the defects into systematic defect bins or random defect bins, and wherein the method further comprises sampling the defects from the bins for defect review.

7. The method of claim 1, wherein said classifying further comprises dividing one of the blocks into multiple regions within the block to separate different types of defects into different bins based on the multiple regions in which the positions of the defects are located.

8. The method of claim 1, wherein said classifying further comprises identifying defects located in regions of the blocks that are prone to nuisance defects as the nuisance detects and eliminating the detects identified as the nuisance defects from results of inspection of the wafer.

9. The method of claim 1, further comprising monitoring the ratio of the numbers of the defects detected in at least two of the different types of blocks.

10. The method of claim 1, further comprising correlating the positions of the defects within the blocks with a bit map.

11. The method of claim 1, wherein said classifying further comprises correlating the positions of the defects within the blocks with a bit map and determining types of the defects based on results of said correlating.

12. The method of claim 1, wherein said classifying further comprises correlating the positions of the defects within the blocks with a bit map, determining types of defects based on results of said correlating, and eliminating one or more of the types of the defects from results of inspection of the wafer.

13. The method of claim 1, further comprising determining one or more problems with one or more processes used to form the memory device area on the wafer based on results of said classifying.

14. The method of claim 1, further comprising determining one or more parameters of one or more processes to be performed on the memory device area based on the positions of the defects.

15. The method of claim 1, further comprising determining one or more parameters of one or more processes to be performed on the memory device area based on distribution of the defects on the memory device area and the positions of the defects.

16. The method of claim 1, further comprising altering one or more parameters of a process used by the inspection system to generate the inspection data based on results of said classifying such that at least two of the different types of blocks in the memory device area are inspected with different sensitivities.

17. The method of claim 1, wherein the method is performed by the inspection system during an inspection process performed by the inspection system for the wafer on which the memory device area is formed.

18. The method of claim 1, wherein determining the positions of the inspection data comprises determining the positions of the inspection data in design data space, and wherein determining the positions of the defects comprises determining the positions of the defects with respect to the predetermined location in the design data space.

19. The method of claim 1, wherein determining the positions of the inspection data comprises determining the positions of the inspection data in inspection data space, and wherein determining the positions of the defects comprises determining the positions of the defects with respect to the predetermined location in the inspection data space.

20. A non-transitory computer-readable medium storing program instructions executable on a computer system for performing a computer-implemented method for classifying defects detected in a memory device area on a wafer, wherein the computer-implemented method comprises:

using the computer system to perform the following steps;

determining positions of inspection data acquired for the memory device area by an inspection system, wherein the memory device area comprises different types of blocks, and wherein the inspection data comprises data for defects detected in the memory device area;

determining positions of the defects with respect to a predetermined location within the blocks in which the defects are located based on the positions of the inspection data; and

classifying the defects based on the positions of the defects within the blocks, wherein said classifying comprises determining a ratio of the numbers of the defects detected in at least two of the different types of blocks and classifying the defects in the at least two of the different types of blocks based on the ratio.

21. A system configured to classify defects detected in a memory device area on a wafer, comprising:

an inspection subsystem configured to acquire inspection data for the memory device area formed on the wafer, wherein the memory device area comprises different types of blocks, and wherein the inspection data comprises data for defects detected in the memory device area; and

a computer subsystem configured for;

determining positions of the inspection data;

determining positions of the defects with respect to a predetermined location within the blocks in which the defects are located based on the positions of the inspection data; and

classifying the defects based on the positions of the defects within the blocks, wherein said classifying comprises determining a ratio of the numbers of the defects detected in at least two of the different types of blocks and classifying the defects in the at least two of the different types of blocks based on the ratio.

22. The system of claim 21, wherein the predetermined location comprises a center or a corner of the blocks.

23. The system of claim 21, wherein the computer subsystem is further configured for reporting x, y addresses of the different types of blocks within the memory device area and the positions of the defects within the blocks, and wherein the positions of the defects within the blocks comprise x, y locations with respect to the predetermined location within the blocks.

24. The system of claim 21, wherein said classifying further comprises classifying the defects based on the positions of the defects within the blocks and the types of the blocks in which the defects are located.

25. The system of claim 21, wherein said classifying further comprises determining if the defects are systematic defects.

26. The system of claim 21, wherein said classifying further comprises stacking the inspection data for multiple blocks having the same type to separate the defects into systematic defect bins or random defect bins, and wherein the computer subsystem is further configured for sampling the defects from the bins for defect review.

27. The system of claim 21, wherein said classifying further comprises dividing one of the blocks into multiple regions within the block to separate different types of defects into different bins based on the multiple regions in which the positions of the defects are located.

28. The system of claim 21, wherein said classifying further comprises identifying defects located in regions of the blocks that are prone to nuisance defects as the nuisance defects and eliminating the defects identified as the nuisance defects from results of inspection of the wafer.

29. The system of claim 21, wherein the computer subsystem is further configured for monitoring the ratio of the numbers of the defects detected in at least two of the different types of blocks.

30. The system of claim 21, wherein the computer subsystem is further configured for correlating the positions of the defects within the blocks with a bit map.

31. The system of claim 21, wherein said classifying further comprises correlating the positions of the defects within the blocks with a bit map and determining types of the defects based on results of said correlating.

32. The system of claim 21, wherein said classifying further comprises correlating the positions of the defects within the blocks with a bit map, determining types of the defects based on results of said correlating, and eliminating one or more of the types of the defects from results of inspection of the wafer.

33. The system of claim 21, wherein the computer subsystem is further configured for determining one or more problems with one or more processes used to form the memory device area on the wafer based on results of said classifying.

34. The system of claim 21, wherein the computer subsystem is further configured for determining one or more parameters of one or more processes to be performed on the memory device area based on the positions of the defects.

35. The system of claim 21, wherein the computer subsystem is further configured for determining one or more parameters of one or more processes to be performed on the memory device area based on distribution of the defects on the memory device area and the positions of the defects.

36. The system of claim 21, wherein the computer subsystem is further configured for altering one or more parameters of a process used by the inspection subsystem to generate the inspection data based on results of said classifying such that at least two of the different types of blocks in the memory device area are inspected with different sensitivities.

37. The system of claim 21, wherein the computer subsystem is further configured for performing determining the positions of the inspection data, determining the positions of the defects, and classifying the defects during an inspection process performed by the inspection subsystem for the wafer on which the memory device area is formed.

38. The system of claim 21, wherein determining the positions of the inspection data comprises determining the positions of the inspection data in design data space, and wherein determining the positions of the defects comprises determining the positions of the defects with respect to the predetermined location in the design data space.

39. The system of claim 21, wherein determining the positions of the inspection data comprises determining the positions of the inspection data in inspection data space, and wherein determining the positions of the defects comprises determining the positions of the defects with respect to the predetermined location in the inspection data space.

40. A computer-implemented method for classifying defects detected in a memory device area on a wafer, comprising:

using a computer system to perform the following steps;

determining positions of inspection data acquired for the memory device area by an inspection system, wherein the memory device area comprises different types of blocks, and wherein the inspection data comprises data for defects detected in the memory device area;

determining positions of the defects with respect to a predetermined location within the blocks in which the defects are located based on the positions of the inspection data;

classifying the defects based on the positions of the defects within the blocks; and

monitoring a ratio of the numbers of the defects detected in at least two of the different types of blocks.

41. A non-transitory computer-readable medium storing program instructions executable on a computer system for performing a computer-implemented method for classifying defects detected in a memory device area on a wafer, wherein the computer-implemented method comprises:

using the computer system to perform the following steps;

determining positions of inspection data acquired for the memory device area by an inspection system, wherein the memory device area comprises different types of blocks, and wherein the inspection data comprises data for defects detected in the memory device area;

determining positions of the defects with respect to a predetermined location within the blocks in which the defects are located based on the positions of the inspection data;

classifying the defects based on the positions of the defects within the blocks; and

monitoring a ratio of the numbers of the defects detected in at least two of the different types of blocks.

42. A system configured to classify defects detected in a memory device area on a wafer, comprising:

an inspection subsystem configured to acquire inspection data for the memory device area formed on the wafer, wherein the memory device area comprises different types of blocks, and wherein the inspection data comprises data for defects detected in the memory device area; and

a computer subsystem configured for;

determining positions of the inspection data;

determining positions of the defects with respect to a predetermined location within the blocks in which the defects are located based on the positions of the inspection data;

classifying the defects based on the positions of the defects within the blocks; and

monitoring a ratio of the numbers of the defects detected in at least two of the different types of blocks.

43. The system of claim 42, wherein the predetermine location comprises a center or a corner of the blocks.

44. The system of claim 42, wherein the computer subsystem is further configured for reporting x, y addresses of the different types of blocks within the memory device area and the positions of the defects within the blocks, and wherein the positions of the defects within the blocks comprise x, y locations with respect to the predetermined location within the blocks.

45. The system of claim 42, wherein said classifying comprises classifying the defects based on the positions of the defects within the blocks and the types of the blocks in which the defects are located.

46. The system of claim 42, wherein said classifying comprises determining if the defects are systematic defects.

47. The system of claim 42, wherein said classifying comprises stacking the inspection data for multiple blocks having the same type to separate the defects into systematic defect bins or random defect bins, and wherein the computer subsystem is further configured for sampling the defects from the bins for defect review.

48. The system of claim 42, wherein said classifying comprises dividing one of the blocks into multiple regions within the block to separate different types of defects into different bins based on the multiple regions in which the positions of the defects are located.

49. The system of claim 42, wherein said classifying comprises identifying defects located in regions of the blocks that are prone to nuisance defects as the nuisance defects and eliminating the defects identified as the nuisance defects from results of inspection of the wafer.

50. The system of claim 42, wherein said classifying comprises determining the ratio of the numbers of the defects detected in at least two of the different types of blocks and classifying the defects in the at least two of the different types of blocks based on the ratio.

51. The system of claim 42, wherein the computer subsystem is further configured for correlating the positions of the defects within the blocks with a bit map.

52. The system of claim 42, wherein said classifying comprises correlating the positions of the defects within the blocks with a bit map and determining types of the defects based on results of said correlating.

53. The system of claim 42, wherein said classifying comprises correlating the positions of the defects within the blocks with a bit map, determining types of the defects based on results of said correlating, and eliminating one or more of the types of the defects from results of inspection of the wafer.

54. The system of claim 42, wherein the computer subsystem is further configured for determining one or more problems with one or more processes used to form the memory device area on the wafer based on results of said classifying.

55. The system of claim 42, wherein the computer subsystem is further configured for determining one or more parameters of one or more processes to be performed on the memory device area based on the positions of the defects.

56. The system of claim 42, wherein the computer subsystem is further configured for determining one or more parameters of one or more processes to be performed on the memory device area based on distribution of the defects on the memory device area and the positions of the defects.

57. The system of claim 42, wherein the computer subsystem is further configured for altering one or more parameters of a process used by the inspection subsystem to generate the inspection data based on results of said classifying such that at least two of the different types of blocks in the memory device area are inspected with different sensitivities.

58. The system of claim 42, wherein the computer subsystem is further configured for performing determining the positions of the inspection data, determining the positions of the defects, classifying the defects, and monitoring the ratio during an inspection process performed by the inspection subsystem for the wafer on which the memory device area is formed.

59. The system of claim 42, wherein determining the positions of the inspection data comprises determining the positions of the inspection data in design data space, and wherein determining the positions of the defects comprises determining the positions of the defects with respect to the predetermined location in the design data space.

60. The system of claim 42, wherein determining the positions of the inspection data comprises determining the positions of the inspection data in inspection data space, and wherein determining the positions of the defects comprises determining the positions of the defects with respect to the predetermined location in the inspection data space.