Method and structure for enabling high aspect ratio sacrificial gates

• US 9,659,779 B2
• Filed: 10/27/2014
• Issued: 05/23/2017
• Est. Priority Date: 06/18/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jung, Ryan O., Shearer, Jeffrey C., Sporre, John R., Teehan, Sean, Cheng, Kangguo, Lie, Fee Li
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US14/524,279
• Publication Number:
  US 20150372127A1
• Time in Patent Office: 939 Days
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.

Claims

1. A semiconductor structure comprising:

a plurality of functional gate structures located on a surface of a substrate;

a dielectric spacer comprising a first dielectric material and located along an entirety of a pair of opposing sidewalls of each functional gate structure of said plurality of functional gate structures; and

a second dielectric material located on each end portion of each functional gate structure and contacting an entirety of each end portion of said dielectric spacer, wherein said second dielectric material comprises a different dielectric material than said first dielectric material of said dielectric spacer and wherein said second dielectric material is entirely orthogonal to said dielectric spacer and each functional gate structure, said second dielectric material having a first sidewall surface in contact with a sidewall surface of each functional gate structure, and a second sidewall surface opposite said first sidewall surface contacting a planarization dielectric layer, said planarization dielectric layer is entirely separated from each functional gate structure by said dielectric spacer and said second dielectric material.

2. The semiconductor structure of claim 1, wherein said substrate comprises an insulator layer and wherein at least one semiconductor fin is present on said insulator layer, and wherein each functional gate straddles a portion of said at least one semiconductor fin and said dielectric spacer straddles another portion of said at least one semiconductor fin.

3. The semiconductor structure of claim 1, wherein said dielectric spacer comprises a low k dielectric material.

4. The semiconductor structure of claim 2, further comprising epitaxial semiconductor material portions located on still other portions of said at least one semiconductor fin and on each side of the functional gate structure, wherein said epitaxial semiconductor material portions are doped with an n-type dopant.

5. The semiconductor structure of claim 2, further comprising epitaxial semiconductor material portions located on still other portions of said at least one semiconductor fin and on each side of the functional gate structure, wherein said epitaxial semiconductor material portions are doped with a p-type dopant.

6. The semiconductor structure of claim 1, wherein said planarization dielectric layer has a topmost surface that is coplanar with a topmost surface of each functional gate structure and a topmost surface of both of said dielectric spacer and said second dielectric material.

7. The semiconductor structure of claim 1, wherein a bottommost surface of said second dielectric material directly contacts a topmost surface of said substrate.

8. The semiconductor structure of claim 1, wherein a bottommost surface of said dielectric spacer directly contacts a topmost surface of said substrate.

9. The semiconductor structure of claim 1, wherein each of said functional gate structures has a height from 50 nm to 200 nm, and a width from 5 nm to 30 nm.

10. The semiconductor structure of claim 2, wherein said at least one semiconductor fin comprises a single crystalline semiconductor material.

11. The semiconductor structure of claim 10, wherein said single crystalline semiconductor material comprises undoped silicon.

12. The semiconductor structure of claim 1, wherein each of said plurality of functional gate structures comprises, from bottom to top, a gate dielectric material and a gate conductor material.

13. The semiconductor structure of claim 12, further comprising a gate cap material located on said gate conductor material.

14. The semiconductor structure of claim 3, wherein said second dielectric material comprises a high k dielectric material.

15. The semiconductor structure of claim 1, wherein said planarization dielectric layer comprises a third dielectric material that differs from the first and second dielectric materials.

16. The semiconductor structure of claim 1, wherein said planarization dielectric layer comprises undoped or doped silicate glass.