Systems and methods for dynamic semiconductor process scheduling
First Claim
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1. A method comprising:
- analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool comprising an expected time to transfer a first wafer from a wafer handling chamber to a first process module, an expected time to transfer the first wafer from the first process module to the wafer handling chamber, an expected time to transfer a second wafer from the wafer handling chamber to a second process module, and an expected time to transfer the second wafer from the second process module to the wafer handling chamber, the semiconductor processing tool including the first process module and the second process module; and
automatically generating, by a computer program, a wafer processing plan based on the analysis, wherein the wafer processing plan, when executed by the processing tool, causes the semiconductor processing tool to;
load the first wafer into the first process module;
load the second wafer into the second process module;
unload the first wafer from the first process module after loading the second wafer into the second process module;
load a third wafer into the first process module after unloading the first wafer form the first process module; and
unload the second wafer from the second process module after loading the third wafer into the first process module;
wherein the semiconductor processing tool includes the wafer handling chamber in communication with the first process module and the second process module, andwherein execution of the wafer processing plan by the semiconductor processing tool causes an idle time for the wafer handling chamber prior to unloading the first wafer from the first process module to be about equal to an idle time for the wafer handling chamber after loading the third wafer into the first process module, andwherein the computer program measures an actual time to complete the steps of load the first wafer, load the second wafer, unload the first wafer, load the third wafer, and unload the second wafer, and automatically adjusts future wafer processing plans based on the actual time to complete steps of load the first wafer, load the second wafer, unload the first wafer, load the third wafer, and unload the second wafer.
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Abstract
Embodiments of the present disclosure can help increase throughput and reduce resource conflicts and delays in semiconductor processing tools. An exemplary method according to various aspects of the present disclosure includes analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool, the semiconductor processing tool including a first process module and a second process module.
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Citations
37 Claims
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1. A method comprising:
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analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool comprising an expected time to transfer a first wafer from a wafer handling chamber to a first process module, an expected time to transfer the first wafer from the first process module to the wafer handling chamber, an expected time to transfer a second wafer from the wafer handling chamber to a second process module, and an expected time to transfer the second wafer from the second process module to the wafer handling chamber, the semiconductor processing tool including the first process module and the second process module; and automatically generating, by a computer program, a wafer processing plan based on the analysis, wherein the wafer processing plan, when executed by the processing tool, causes the semiconductor processing tool to; load the first wafer into the first process module; load the second wafer into the second process module; unload the first wafer from the first process module after loading the second wafer into the second process module; load a third wafer into the first process module after unloading the first wafer form the first process module; and unload the second wafer from the second process module after loading the third wafer into the first process module; wherein the semiconductor processing tool includes the wafer handling chamber in communication with the first process module and the second process module, and wherein execution of the wafer processing plan by the semiconductor processing tool causes an idle time for the wafer handling chamber prior to unloading the first wafer from the first process module to be about equal to an idle time for the wafer handling chamber after loading the third wafer into the first process module, and wherein the computer program measures an actual time to complete the steps of load the first wafer, load the second wafer, unload the first wafer, load the third wafer, and unload the second wafer, and automatically adjusts future wafer processing plans based on the actual time to complete steps of load the first wafer, load the second wafer, unload the first wafer, load the third wafer, and unload the second wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A system comprising:
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a semiconductor processing tool including a first process module and a second process module; and a computer system comprising; a processor; and a memory coupled to the processor and storing instructions that, in response to execution by the processor, cause the processor to perform operations comprising; analyzing a plurality of expected times to complete each of a respective plurality of actions to be performed by the semiconductor processing tool comprising an expected time to transfer a first wafer from a wafer handling chamber to a first process module, an expected time to transfer the first wafer from the first process module to the wafer handling chamber, an expected time to transfer a second wafer from the wafer handling chamber to a second process module, and an expected time to transfer the second wafer from the second process module to the wafer handling chamber, the semiconductor processing tool including the first process module and the second process module; and automatically generating a wafer processing plan based on the analysis, wherein the wafer processing plan, when executed by the processing tool, is configured to cause the semiconductor processing tool to; load the first wafer into the first process module; load the second wafer into the second process module; unload the first wafer from the first process module after loading the second wafer into the second process module; load a third wafer into the first process module after unloading the first wafer from the first process module; and unload the second wafer from the second process module after loading the third wafer into the first process module; wherein the semiconductor processing tool includes the wafer handling chamber in communication with the first process module and the second process module, and wherein execution of the wafer processing plan by the semiconductor processing tool causes an idle time for the wafer handling chamber prior to unloading the first wafer from the first process module to be about equal to an idle time for the wafer handling chamber after loading the third wafer into the first process module, and wherein the wafer computer program measures an actual time to complete the steps of load the first wafer, load the second wafer, unload the first wafer, load the third wafer, and unload the second wafer, and automatically adjusts future wafer processing plans based on actual time to complete load the first wafer, load the second wafer, unload the first wafer, load the third wafer, and unload the second wafer. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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Specification