Stiffened wires for offset BVA

• US 9,659,848 B1
• Filed: 03/31/2016
• Issued: 05/23/2017
• Est. Priority Date: 11/18/2015
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Villavicencio, Grant, Lee, Sangil, Alatorre, Roseann, Delacruz, Javier A., McGrath, Scott
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US15/086,899
• Publication Number:
  US 20170141020A1
• Time in Patent Office: 418 Days
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/1329 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/133 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 23/043 : the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
• CPC Class Codes: H01L 23/053 : the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1438 : Flash memory
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/15333 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

Claims

1. A component, comprising:

a generally planar element having oppositely-facing first and second surfaces extending in first and second transverse directions, the generally planar element having a plurality of contacts at the first surface;

a reinforcing dielectric layer overlying the first surface of the generally planar element;

an encapsulation overlying the reinforcing dielectric layer, the encapsulation having a major surface facing away from the first surface of the generally planar element; and

a plurality of wire bonds, each wire bond having a base joined with a contact of the plurality of contacts, and a tip remote from the base at the major surface of the encapsulation, the wire bonds having first portions extending within at least a portion of the reinforcing dielectric layer and second portions extending within the encapsulation, the first portions of at least some of the wire bonds having bends that change an extension direction of the respective wire bond in at least one of the first and second directions,

wherein the reinforcing dielectric layer has protruding regions surrounding respective wire bonds of the plurality of wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions, the peak heights of the protruding regions coinciding with points of contact between the reinforcing dielectric layer and individual ones of the wire bonds.

2. The component of claim 1, wherein the component comprises a microelectronic package, the microelectronic package further including a microelectronic element having oppositely-facing top and bottom surfaces, the bottom surface facing the first surface of the generally planar element and mechanically coupled therewith, and wherein the major surface of the encapsulation overlies the top surface of the microelectronic element.

3. The microelectronic package of claim 2, wherein the tips of a subset of the at least some of the wire bonds overlie the top surface of the microelectronic element.

4. The microelectronic package of claim 2, wherein the dielectric layer overlies the top surface of the microelectronic element.

5. The microelectronic package of claim 2, further comprising a plurality of upper terminals joined with corresponding ones of the wire bonds, the upper terminals at the major surface of the encapsulation and configured to be electrically connected with conductive elements of a component external to the microelectronic package.

6. A microelectronic assembly comprising the microelectronic package of claim 2, the microelectronic assembly further comprising a second component having terminals, the tips of the wire bonds being electrically connected to the terminals.

7. A system comprising the microelectronic package of claim 2 and one or more other electronic components electrically connected to the microelectronic package.

8. The system of claim 7, further comprising a housing, the microelectronic package and the one or more other electronic components being assembled with the housing.

9. The component of claim 1, wherein the bases of the wire bonds define a first minimum pitch between adjacent ones of the bases, and the tips of the wire bonds define a second minimum pitch between adjacent ones of the tips, the second minimum pitch being greater than the first minimum pitch.

10. The component of claim 1, wherein the reinforcing dielectric layer comprises a first reinforcing dielectric layer overlying the first surface of the generally planar element, and a second reinforcing dielectric layer overlying the first reinforcing dielectric layer and defining an upper surface of the reinforcing dielectric layer.

11. The component of claim 1, wherein the bends of the first portions of the wire bonds are first bends, and the at least some of the wire bonds each include a second bend changing the extension direction of the respective wire bond in at least one of the first and second directions.

12. The component of claim 11, wherein at least some of the second bends of the wire bonds are disposed within the reinforcing dielectric layer.

13. The component of claim 1, wherein the reinforcing dielectric layer is configured to maintain the position of the tips of the wire bonds in a third direction perpendicular to the first and second directions when a force is applied to the tips of the wire bonds in the third direction.

14. A microelectronic package, comprising:

a generally planar element having oppositely-facing first and second surfaces extending in first and second transverse directions, the generally planar element having a plurality of contacts at the first surface;

a reinforcing dielectric layer overlying the first surface of the generally planar element;

an encapsulation overlying the reinforcing dielectric layer, the encapsulation having a major surface facing away from the first surface of the generally planar element;

a microelectronic element having oppositely-facing top and bottom surfaces, the bottom surface facing the first surface of the generally planar element and mechanically coupled therewith, the major surface of the encapsulation overlying the top surface of the microelectronic element; and

a plurality of wire bonds, each wire bond having a base joined with a contact of the plurality of contacts, and a tip remote from the base at the major surface of the encapsulation, the wire bonds having first portions extending within at least a portion of the reinforcing dielectric layer and second portions extending within the encapsulation, the first portions of at least some of the wire bonds having bends that change an extension direction of the respective wire bond in at least one of the first and second directions,

wherein the reinforcing dielectric layer extends to a greater peak height from the first surface of the generally planar element than the microelectronic element.

15. The microelectronic package of claim 14, wherein the tips of a subset of the at least some of the wire bonds overlie the top surface of the microelectronic element.

16. The microelectronic package of claim 14, wherein the bends of the first portions of the wire bonds are first bends, and the at least some of the wire bonds each include a second bend changing the extension direction of the respective wire bond in at least one of the first and second directions.

17. A method of forming a component, comprising:

providing a generally planar element having oppositely-facing first and second surfaces extending in first and second transverse directions, the generally planar element having a plurality of contacts at the first surface;

forming a plurality of wire bonds, each wire bond having a base joined with a contact of the plurality of contacts and a tip remote from the base, first portions of at least some of the wire bonds having bends that change an extension direction of the respective wire bond in at least one of the first and second directions;

forming a reinforcing dielectric layer overlying the first surface of the generally planar element, the first portions of the wire bonds extending within at least a portion of the reinforcing dielectric layer, the reinforcing dielectric layer having protruding regions surrounding respective wire bonds of the plurality of wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions, the peak heights of the protruding regions coinciding with points of contact between the reinforcing dielectric layer and individual ones of the wire bonds;

flowing an encapsulation between the reinforcing dielectric layer and a lower surface of a molding film into which tips of the wire bonds extend, the encapsulation having a major surface facing away from the first surface of the generally planar element, the wire bonds having second portions extending within the encapsulation; and

removing the molding film from the encapsulation, the tips of the wire bonds being at the major surface of the encapsulation.

18. The method of claim 17, wherein the component comprises a microelectronic package, the microelectronic package further including a microelectronic element having oppositely-facing top and bottom surfaces, the bottom surface facing the first surface of the generally planar element and mechanically coupled therewith, and wherein the major surface of the encapsulation overlies the top surface of the microelectronic element.

19. The method of claim 17, wherein the protruding regions wick up the wire bonds and reach their respective peak heights before the flowing of the encapsulation.

20. The method of claim 19, wherein the peak heights of the protruding regions do not reach the tips of the wire bonds.

21. The method of claim 17, further comprising, before the flowing of the encapsulation, depositing the molding film overlying the reinforcing dielectric layer, the tips of the wire bonds extending into the molding film.