Semiconductor devices including stair step structures, and related methods
First Claim
1. A vertical memory device comprising:
- an elongated vertical memory array block including vertical strings of memory cells extending through at least thirty-two conductive tiers; and
a stair step structure including contact regions of respective conductive tiers of the at least thirty-two conductive tiers,wherein the elongated vertical memory array block has a lateral width of about 5 μ
m or less.
7 Assignments
0 Petitions
Accused Products
Abstract
Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
37 Citations
20 Claims
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1. A vertical memory device comprising:
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an elongated vertical memory array block including vertical strings of memory cells extending through at least thirty-two conductive tiers; and a stair step structure including contact regions of respective conductive tiers of the at least thirty-two conductive tiers, wherein the elongated vertical memory array block has a lateral width of about 5 μ
m or less. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor device comprising:
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a memory array block including at least sixteen continuous conductive tiers and two stair step structures defining contact regions to the at least sixteen continuous conductive tiers, the two stair step structures located between longitudinal ends and between two longitudinal portions of the at least sixteen continuous conductive tiers of the memory array block; and sixteen access lines electrically coupled to respective contact regions defined by the two stair step structures, wherein a portion of the memory array block lacks a stair step structure and is located between the two stair step structures. - View Dependent Claims (10, 11)
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12. A method of forming a semiconductor device structure, the method comprising:
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forming a stack of alternating conductive tiers and insulating materials; patterning the stack of alternating conductive tiers and insulating materials to form an elongated memory array block; and forming a stair step structure between longitudinal ends of the elongated memory array block and between lateral side surfaces of the elongated memory array block to define contact regions of respective conductive tiers of the stack of alternating conductive tiers and insulating materials, wherein the alternating conductive tiers of the stack are continuous from one longitudinal side of the stair step structure to an opposing longitudinal side of the stair step structure. - View Dependent Claims (13, 14, 15, 16, 17)
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- 18. A method of operating a semiconductor device, the method comprising accessing a memory cell of a three-dimensional memory array block defined by an elongated stack of continuous conductive tiers, the three-dimensional memory array block including a stair step structure positioned between longitudinal ends of the three-dimensional memory array block, the stair step structure defining contact regions for electrically accessing respective conductive tiers of the elongated stack of continuous conductive tiers, wherein the stair step structure is positioned longitudinally between a first portion of vertical strings of memory cells of the three-dimensional memory array block including the accessed memory cell and a second portion of vertical strings of memory cells of the three-dimensional memory array block.
Specification