HKMG high voltage CMOS for embedded non-volatile memory
First Claim
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1. A method of forming an integrated circuit (IC) comprising:
- providing a semiconductor substrate comprising a first region and a second region;
forming a non-volatile memory (NVM) device over the first region;
forming a protective sacrificial layer that covers the NVM device while leaving the second region exposed;
with the protective sacrificial layer in place over the NVM device, selectively forming a high voltage (HV) gate insulating layer over the semiconductor substrate in the second region;
forming a gate oxide layer over the protective sacrificial layer and over the HV gate insulating layer;
forming a HV high-κ
metal gate (HKMG) transistor over the HV gate insulating layer; and
forming one or more HKMG CMOS devices in the second region.
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Abstract
The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.
20 Citations
20 Claims
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1. A method of forming an integrated circuit (IC) comprising:
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providing a semiconductor substrate comprising a first region and a second region; forming a non-volatile memory (NVM) device over the first region; forming a protective sacrificial layer that covers the NVM device while leaving the second region exposed; with the protective sacrificial layer in place over the NVM device, selectively forming a high voltage (HV) gate insulating layer over the semiconductor substrate in the second region; forming a gate oxide layer over the protective sacrificial layer and over the HV gate insulating layer; forming a HV high-κ
metal gate (HKMG) transistor over the HV gate insulating layer; andforming one or more HKMG CMOS devices in the second region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming an integrated circuit (IC) comprising:
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providing a semiconductor substrate comprising a memory region, a high-voltage transistor region, and a logic region; forming a pair of split-gate flash memory cell structures over the memory region, wherein the pair of split-gate flash memory cell structures includes a pair of select gates spaced on opposite sides of a common source/drain region, and a pair of memory gates disposed about outer sidewalls of the pair of select gates, respectively; forming a protective sacrificial layer that covers the pair of split-gate flash memory cell structures while leaving the high-voltage transistor region and logic region exposed; with the protective sacrificial layer in place over the pair of split-gate flash memory cell structures, forming a high-voltage gate structure of a high-voltage transistor over the high-voltage transistor region and forming a logic gate structure over the logic transistor region; after the high-voltage gate structure and logic gate structure have been formed, removing the protective sacrificial layer from over the split-gate flash memory cell; and performing a chemical mechanical planarization (CMP) operation to planarize upper surfaces of the select gates with an upper surface of the high-voltage gate structure and upper surface of the logic gate structure. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method of forming an integrated circuit (IC) comprising:
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providing a semiconductor substrate comprising a memory region, a high-voltage transistor region, and a logic region; forming a non-volatile memory cell structure over the memory region; forming a protective sacrificial layer that covers the non-volatile memory cell structure while leaving the high-voltage transistor region and logic region exposed; with the protective sacrificial layer in place over the non-volatile memory cell structure, forming a first oxide layer over the protective sacrificial layer, the high-voltage transistor region, and the logic region; with the protective sacrificial layer in place over the non-volatile memory cell structure, forming a high-voltage gate structure of a high-voltage transistor over the high-voltage transistor region and forming a logic gate structure over the logic transistor region; and after the high-voltage gate structure and logic gate structure have been formed, removing the protective sacrificial layer from over the non-volatile memory cell structure. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification