Vertical integration of CMOS electronics with photonic devices

• US 9,659,993 B2
• Filed: 09/10/2014
• Issued: 05/23/2017
• Est. Priority Date: 01/18/2012
• Status: Active Grant

• Current Assignee: Skorpios Technologies Inc.
• Original Assignee: Skorpios Technologies Inc.
• Inventors: Creazzo, Timothy, Marchena, Elton, Dallesasse, John, Krasulick, Stephen B.
• Primary Examiner(s): NIKMANESH, SEAHVOSH J
• Application Number:
  US14/482,650
• Publication Number:
  US 20150123157A1
• Time in Patent Office: 986 Days
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission

Abstract

A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.

Claims

1. A method of fabricating a composite semiconductor structure, the method comprising:

providing a substrate;

providing a photonic die, the photonic die comprising III-V material;

aligning the photonic die with the substrate;

joining the substrate and the photonic die to form a composite substrate; and

processing the composite substrate to form a feature on the photonic die, wherein;

the processing the composite substrate is performed after joining the substrate and the photonic die;

the feature on the photonic die is a stripe region; and

the stripe region is an optical waveguide.

2. The method of fabricating the composite semiconductor structure as recited in claim 1, wherein the processing the composite substrate further includes forming an electrical interconnect on the photonic die.

3. The method of fabricating the composite semiconductor structure as recited in claim 1, further comprising using an alignment tolerance of approximately ±

10 μ

m for aligning the photonic die with the substrate.

4. The method of fabricating the composite semiconductor structure as recited in claim 1, wherein the processing the composite substrate further forms an optical waveguide on the substrate.

5. The method of fabricating the composite semiconductor structure as recited in claim 1, the method further comprising growing epitaxial layers on the photonic die after joining the substrate and the photonic die to form the composite substrate.

6. The method of fabricating the composite semiconductor structure as recited in claim 1, the method further comprising:

providing an assembly substrate having a base layer and a device layer;

mounting the photonic die on a predetermined portion of the assembly substrate;

aligning the assembly substrate with the substrate to align the photonic die with the substrate; and

removing at least the base layer of the assembly substrate from the composite substrate after the photonic die and the substrate are joined.

7. The method of fabricating the composite semiconductor structure as recited in claim 1, wherein:

the photonic die is a first photonic die; and

the method further comprises;

providing a second photonic die;

mounting the first photonic die and the second photonic die on an assembly substrate; and

aligning the assembly substrate with the substrate.

8. The method of fabricating the composite semiconductor structure as recited in claim 1, wherein the substrate comprises a silicon-on-insulator (SOI) substrate.

9. The method of fabricating the composite semiconductor structure as recited in claim 1, wherein the substrate comprises silicon-based devices.