High-yield fabrication of large-format substrates with distributed, independent control elements

• US 9,660,008 B2
• Filed: 09/09/2015
• Issued: 05/23/2017
• Est. Priority Date: 09/16/2009
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: Semprius, Inc.
• Inventors: Bower, Christopher, Menard, Etienne, Cok, Ronald S., Hamer, John
• Primary Examiner(s): Diaz, Jose R
• Application Number:
  US14/848,477
• Publication Number:
  US 20160056223A1
• Time in Patent Office: 622 Days
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: H10K 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/129 Chiplets
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 71/70 Testing, e.g. accelerated lifetime tests

Abstract

A large-format substrate with distributed control elements is formed by providing a substrate and a wafer, the wafer having a plurality of separate, independent chiplets formed thereon; imaging the wafer and analyzing the wafer image to determine which of the chiplets are defective; removing the defective chiplet(s) from the wafer leaving remaining chiplets in place on the wafer; printing the remaining chiplet(s) onto the substrate forming empty chiplet location(s); and printing additional chiplet(s) from the same or a different wafer into the empty chiplet location(s).

Claims

1. A system comprising:

a wafer of chiplets, the wafer comprising;

a source substrate having an array of regularly-spaced chiplet locations thereon; and

a plurality of chiplets native to the source substrate, each chiplet of the plurality of chiplets disposed on the source substrate in one of the chiplet locations in the array, wherein one or more of the chiplet locations in the array is a removed-chiplet location that is devoid of a chiplet and the removed-chiplet location(s) form an irregular arrangement; and

a storage device, distinct from the plurality of chiplets, for storing a record of locations of chiplets determined to be defective, wherein the locations of the chiplets determined to be defective correspond to the removed-chiplet locations.

2. The system of claim 1, wherein each chiplet of the plurality of chiplets is partially released from the substrate such that each chiplet is connected to the substrate via a micro-bridge of a plurality of micro-bridges.

3. The system of claim 1, wherein each chiplet is connected to the substrate via a micro-bridge of a plurality of micro-bridges.

4. The system of claim 3, wherein each micro-bridge supports a respective chiplet.

5. The system of claim 3, comprising a plurality of anchors on the source substrate, wherein each micro-bridge is connected to an anchor of the plurality of anchors.

6. The system of claim 5, comprising a buried oxide layer under the plurality of anchors.

7. The system of claim 6, wherein the buried oxide layer is under the chiplet.

8. The system of claim 3, wherein the plurality of micro-bridges connecting the chiplets to the wafer comprise electrical connections.

9. The system of claim 8, wherein the micro-bridges comprise selectively-doped semiconductor material, thereby providing the electrical connections.

10. The system of claim 8, wherein the electrical connections comprise metal lines.

11. The system of claim 8, wherein respective ones of the plurality of chiplets are coupled to the storage device via the electrical connections of respective ones of the plurality of micro-bridges.

12. The system of claim 1, comprising wires connected to the plurality of chiplets.

13. The system of claim 1, comprising electrical connections to each chiplet of the plurality of chiplets.

14. The system of claim 1, comprising test circuitry for electrically stimulating the plurality of chiplets to test chiplet functionality.

15. The system of claim 1, wherein the one or more storage devices are one or more storage registers.

16. The system of claim 1, wherein the chiplets are organic light emitting diodes.

17. The system of claim 1, wherein the chiplets have a thickness of less than 20 micrometers.

18. The system of claim 1, wherein the chiplets are configured to control organic light emitting diodes.

19. The system of claim 1, wherein the chiplets are arranged to control electrical current to pixels.

20. The system of claim 1, wherein remaining chiplets of the plurality of chiplets do not form a regularly-spaced array.

21. The system of claim 1, wherein the storage device is on the wafer.