Concentric capacitor structure

• US 9,660,019 B2
• Filed: 03/21/2016
• Issued: 05/23/2017
• Est. Priority Date: 03/02/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ho-Hsiang, Yeh, Tzu-Jin, Lu, Ying-Ta, Liao, Hsien-Yuan, Lin, Chi-Hsien
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US15/075,759
• Publication Number:
  US 20160204191A1
• Time in Patent Office: 428 Days
• Field of Search: 257532, 257309, 257306, 257415, 257312, 257418, 257296, 257534, 438689, 438 52, 438253, 438240
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/88 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.

Claims

1. A structure comprising:

a semiconductor substrate comprising a first routing layer, a second routing layer, a third routing layer and a fourth routing layer;

at least one concentric capacitor formed on the semiconductor substrate, wherein each of the at least one concentric capacitors comprises;

a first plurality of capacitive perimeter plates formed in the first routing layer and a third plurality of capacitive perimeter plates formed in the third routing layer, the first plurality of capacitive perimeter plates and the third plurality of capacitive perimeter plates extending in a first direction;

a second plurality of capacitive perimeter plates formed in the second routing layer and a fourth plurality of capacitive perimeter plates formed in the fourth routing layer, the second plurality of capacitive perimeter plates and the fourth plurality of capacitive perimeter plates extending in a second direction, wherein the second direction is different than the first direction, wherein a first set of the first plurality of capacitive perimeter plates is electrically coupled to a first set of the second plurality of capacitive perimeter plates to define an outer concentric capacitive plate, and wherein a second set of the first plurality of capacitive perimeter plates is electrically coupled to a second set of the second plurality of capacitive perimeter plates to define an inner concentric capacitive plate;

a first plurality of capacitive cross-plates formed in the first routing layer, the first plurality of capacitive cross-plates extending longitudinally in the first direction, wherein each of the first plurality of capacitive cross-plates at least partially overlaps the second plurality of capacitive perimeter plates formed in the second routing layer, and wherein each of the first plurality of capacitive cross-plates are electrically coupled to at least one of the second plurality of capacitive perimeter plates by a first set of inter-layer vias, thereby increasing a capacitance of the at least one concentric capacitor; and

a switching mechanism configured to selectively couple one of the outer concentric capacitive plate or the inner concentric capacitive plate to a signal source.

2. The structure of claim 1, comprising a second plurality of capacitive cross-plates formed in the second routing layer, the second plurality of capacitive cross-plates extending longitudinally in the second direction, wherein each of the second plurality of capacitive cross-plates at least partially overlaps the first plurality of capacitive perimeter plates formed in the first routing layer, and wherein each of the second plurality of capacitive cross-plates are electrically coupled to at least one of the first plurality of capacitive perimeter plates by a second set of inter-layer vias, thereby increasing the capacitance of the at least one concentric capacitor.

3. The structure of claim 2, wherein the third plurality of capacitive perimeter plates located symmetrically with respect to the first plurality of capacitive perimeter plates, wherein a first set of the third plurality of capacitive perimeter plates are electrically coupled to the outer concentric capacitive plate, and wherein a second set of the third plurality of capacitive perimeter plates are electrically coupled to the inner concentric capacitive plate.

4. The structure of claim 3, further comprising a third plurality of capacitive cross-plates formed in the third routing layer, the third plurality of capacitive cross-plates extending longitudinally in the first direction, wherein each of the third plurality of capacitive cross-plates at least partially overlaps the second plurality of capacitive perimeter plates formed in the second routing layer, and wherein each of the third plurality of capacitive cross-plates are electrically coupled to at least one of the second plurality of capacitive perimeter plates by a third set of inter-layer vias, thereby increasing the capacitance of the at least one concentric capacitor.

5. The structure of claim 4, wherein, the fourth plurality of capacitive perimeter plates located symmetrically with respect to the second plurality of capacitive perimeter plates, wherein a first set of the fourth plurality of capacitive perimeter plates is electrically coupled to the outer concentric capacitive plates and a second set of the fourth plurality of capacitive perimeter plates is electrically coupled to the inner concentric capacitive plates.

6. The structure of claim 5, further comprising a fourth plurality of capacitive cross-plates formed in the fourth routing layer, the fourth plurality of capacitive cross-plates extending longitudinally in the second direction, wherein each of the fourth plurality of capacitive cross-plates at least partially overlaps the first and third pluralities of capacitive perimeter plates, and wherein each of the fourth plurality of capacitive cross-plates are electrically coupled to at least one of the third plurality of capacitive perimeter plates by a fourth set of inter-layer vias, thereby increasing the capacitance of the at least one concentric capacitor.

7. The structure of claim 1, wherein the switching mechanism is selected from the group consisting of metal-oxide-semiconductor field effect transistor (MOSFET), a diode, a bipolar junction transistor (BJT), a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or combinations thereof.

8. A differential capacitive structure, comprising:

a semiconductor substrate comprising a first routing layer and a second routing layer;

a first concentric capacitor bank and a second concentric capacitor bank formed on the semiconductor substrate, each of the concentric capacitor banks comprising;

at least two concentric capacitors formed on the semiconductor substrate, wherein each of the concentric capacitors comprises;

a first plurality of capacitive perimeter plates formed in the first routing layer, the first plurality of capacitive perimeter plates extending in a first direction;

a second plurality of capacitive perimeter plates formed in the second routing layer, the second plurality of capacitive perimeter plates extending in a second direction, wherein the second direction is different than the first direction, wherein a first set of the first plurality of capacitive perimeter plates is electrically coupled to a first set of the second plurality of capacitive perimeter plates to define an outer concentric capacitive plate, and wherein a second set of the first plurality of capacitive perimeter plates is electrically coupled to a second set of the second plurality of capacitive perimeter plates to define an inner concentric capacitive plate; and

a first plurality of capacitive cross-plates formed in the first routing layer, the first plurality of capacitive cross-plates extending longitudinally in the first direction, wherein each of the first plurality of capacitive cross-plates at least partially overlaps the second plurality of capacitive perimeter plates formed in the second routing layer, and wherein each of the first plurality of capacitive cross-plates are electrically coupled to at least one of the second plurality of capacitive perimeter plates, thereby increasing a capacitance of at least one of the outer and inner concentric capacitive plates; and

a switching mechanism configured to selectively couple at least one of the concentric capacitors to a signal source.

9. The differential capacitive structure of claim 8, wherein each of the concentric capacitor banks comprises a second plurality of capacitive cross-plates formed in the second routing layer, the second plurality of capacitive cross-plates extending longitudinally in the second direction, wherein each of the second plurality of capacitive cross-plates at least partially overlaps the first plurality of capacitive perimeter plates formed in the first routing layer, and wherein each of the second plurality of capacitive cross-plates are electrically coupled to at least one of the first plurality of capacitive perimeter plates, thereby increasing the capacitance of at least one of the concentric capacitors.

10. The differential capacitive structure of claim 9, wherein the semiconductor substrate comprises a third routing layer, the structure further comprising a third plurality of capacitive perimeter plates formed on the third routing layer, the third plurality of capacitive perimeter plates extending in the first direction and located symmetrically with respect to the first plurality of capacitive perimeter plates, wherein a first set of the third plurality of capacitive perimeter plates is electrically coupled to the outer concentric capacitive plate, and wherein a second set of the third plurality of capacitive perimeter plates is electrically coupled to the inner concentric capacitive plate.

11. The structure of claim 10, further comprising a third plurality of capacitive cross-plates formed on the third routing layer, the third plurality of capacitive cross-plates extending longitudinally in the first direction, wherein each of the third plurality of capacitive cross-plates at least partially overlaps the second plurality of capacitive perimeter plates formed in the second routing layer, and wherein each of the third plurality of capacitive cross-plates are electrically coupled to at least one of the second plurality of capacitive perimeter plates, thereby increasing the capacitance of at least one the concentric capacitors.

12. The structure of claim 11, wherein the semiconductor substrate comprises a fourth routing layer, the structure further comprising a fourth plurality of capacitive perimeter plates formed on the fourth routing layer, the fourth plurality of capacitive perimeter plates extending in the second direction and located symmetrically with respect to the second plurality of capacitive perimeter plates, wherein a first set of the fourth plurality of capacitive perimeter plates is electrically coupled to the outer concentric capacitive plates and a second set of the fourth plurality of capacitive perimeter plates is electrically coupled to the inner concentric capacitive plates.

13. The differential capacitive structure of claim 8, wherein the switching mechanism is selected from the group consisting of a metal-oxide-semiconductor field effect transistor (MOSFET), a diode, a bipolar junction transistor (BJT), a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or combinations thereof.