Multi-gate device and method of fabrication thereof

• US 9,660,033 B1
• Filed: 01/13/2016
• Issued: 05/23/2017
• Est. Priority Date: 01/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, I-Sheng, Wu, Cheng-Hsien, Yeo, Yee-Chia, Yeh, Chih Chieh
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US14/994,399
• Time in Patent Office: 496 Days
• Field of Search: 257192, 257327, 257401, 257E21409, 257E29022, 257E29128, 257E29345, 438283, 438478
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of semiconductor device fabrication includes providing a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first layer, a second layer over the first layer, and a third layer over the second layer. A gap is formed by removing at least a portion of the second layer from the channel region. A first material is formed in the channel region to form first and second interfacial layer portions, each at least partially wrapping around the first and third layers respectively. A second material is deposited in the channel region to form first and second high-k dielectric layer portions, each at least partially wrapping around the first and second interfacial layer portions. A metal layer including a scavenging material is formed along opposing sidewalls of the first and second high-k dielectric layer portions in the channel region.

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a fin extending from a substrate, the fin having a source/drain region and a channel region, wherein the fin includes a first layer disposed over the substrate, a second layer disposed over the first layer, and a third layer disposed over the second layer;

removing at least a portion of the second layer from the channel region to form a gap between the first and third layers;

forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the first layer and a second interfacial layer portion at least partially wrapping around the third layer;

depositing a second material in the channel region to form a first high-k dielectric layer portion at least partially wrapping around the first interfacial layer portion and a second high-k dielectric layer portion at least partially wrapping around the second interfacial layer portion; and

forming a metal layer along opposing sidewalls of the first and second high-k dielectric layer portions in the channel region, wherein the metal layer includes a scavenging material.

2. The method of claim 1, wherein each of the first and third layers has a rounded profile.

3. The method of claim 2, wherein the rounded profile has a circle shape.

4. The method of claim 1, wherein after the forming of the metal layer, the gap is free of the scavenging material.

5. The method of claim 1, further comprising:

forming the first layer by growing a first silicon germanium layer;

forming the second layer by growing a silicon layer directly on the first silicon germanium layer; and

forming the third layer by growing a second silicon germanium layer directly on the silicon layer.

6. The method of claim 1, further comprising:

after the removing of the at least a portion of the second layer from the channel region, growing a silicon layer on the first and third layers.

7. The method of claim 1, further comprising:

performing an annealing process to the metal layer to cause a scavenging process to the first and second interfacial layer portions.

8. A method, comprising:

forming a fin element including first, second, and third semiconductor layers;

removing at least a portion of the second semiconductor layer from a channel region of the fin element to form a gap between the first and third semiconductor layers;

forming an interposing feature in the channel region, wherein the interposing feature includes;

a first interfacial layer portion at least partially wrapping around the first semiconductor layer;

a first high-k dielectric layer portion at least partially wrapping around the first interfacial layer portion;

a second interfacial layer portion at least partially wrapping around the third semiconductor layer; and

a second high-k dielectric layer portion at least partially wrapping around the second interfacial layer portion; and

depositing a metal layer at least partially wrapping around the interposing feature, wherein the metal layer includes a scavenging material.

9. The method of claim 8, wherein a thickness of the second semiconductor layer is less than twice of a width of a sidewall of the interposing feature.

10. The method of claim 8, further comprising:

etching the first and third semiconductor layers so that each of the first and third semiconductor layers has a rounded profile.

11. The method of claim 10, wherein the rounded profile is a circle.

12. The method of claim 8, wherein after the depositing of the metal layer, the gap is free of the scavenging material.

13. The method of claim 8, further comprising:

performing an annealing process to the metal layer to cause a scavenging process to the first and second interfacial layer portions.

14. The method of claim 13, wherein all areas of the first and second interfacial layer portions are scavenged during the scavenging process.

15. The method of claim 8, further comprising:

forming the first semiconductor layer by growing a first silicon germanium layer;

forming the second semiconductor layer by growing a silicon layer directly on the first silicon germanium layer; and

forming the third semiconductor layer by growing a second silicon germanium layer directly on the silicon layer.

16. The method of claim 8, further comprising:

forming the first semiconductor layer by growing a first germanium layer;

forming the second semiconductor layer by growing a silicon germanium layer directly on the first germanium layer; and

forming the third semiconductor layer by growing a second germanium layer directly on the silicon germanium layer.

17. A method, comprising:

providing a substrate including a fin element, the fin element including a bottom layer disposed over the substrate, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer;

forming a dummy gate structure in a channel region of the fin element;

forming a source/drain feature in a source/drain region of the fin element adjacent to the dummy gate structure;

removing the dummy gate structure to form an opening in the channel region to expose the fin element in the channel region;

removing at least a portion of the middle layer of the fin element exposed in the opening;

forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the bottom layer and a second interfacial layer portion at least partially wrapping around the top layer;

depositing a second material in the channel region to form a first high-k dielectric layer portion at least partially wrapping around the first interfacial layer portion and a second high-k dielectric layer portion at least partially wrapping around the second interfacial layer portion;

forming a metal layer along opposing sidewalls of the first and second high-k dielectric layer portions in the channel region, wherein the metal layer includes a scavenging material; and

causing a scavenging process to the first and second interfacial layer portions by performing an annealing process to the metal layer.

18. The method of claim 17, further comprising:

after the removing of the at least a portion of the middle layer, etching the bottom and top layers in the channel region that each of the bottom and top layers has a rounded profile.

19. The method of claim 18, further comprising:

after the etching of the bottom and top layers, growing a silicon layer on the bottom and top layers.

20. The method of claim 17, wherein all areas of the first and second interfacial layer portions are scavenged during the scavenging process.