Method of manufacturing a semiconductor device with lateral FET cells and field plates

• US 9,660,055 B2
• Filed: 03/01/2016
• Issued: 05/23/2017
• Est. Priority Date: 10/02/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Meiser, Andreas, Poelzl, Martin, Schloesser, Till
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US15/057,800
• Publication Number:
  US 20160181402A1
• Time in Patent Office: 448 Days
• Field of Search: 438287
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins;

providing a first mask covering a first area including first stripe and fin sections and exposing a second area including second stripe and fin sections;

forming channel/body zones in the second fin sections by introducing impurities using the first mask as an implant mask; and

forming recess grooves in the second stripe sections using an etch mask based on the first mask.

2. The method of claim 1, wherein the first mask is used as the etch mask for forming the recess grooves.

3. The method of claim 1, further comprising:

trimming the first mask after introducing the impurities and before forming the recess grooves; and

using the trimmed first mask as the etch mask for forming the recess grooves.

4. The method of claim 1, further comprising:

forming a gate dielectric along sidewalls and top surfaces of the second fin sections after forming the recess grooves in the second stripe sections, the top surfaces being parallel to the first surface.

5. The method of claim 4, further comprising:

implanting impurities into sections of the semiconductor substrate exposed by end faces of the recess grooves, wherein

the gate dielectric is formed by a thermal growth and a cell insulator contemporaneously formed by the thermal growth at exposed end faces of the recess grooves are formed thicker than the gate dielectrics.

6. The method of claim 1, further comprising:

forming buried gate electrodes by filling the recess grooves with conductive material.

7. The method of claim 1, further comprising:

introducing, by using position information contained in a trench mask defining the dielectric stripe structures, contact trenches extending in a second lateral direction orthogonal to longitudinal axes of the dielectric stripe structures parallel to the first surface.

8. The method of claim 7, further comprising:

introducing, by using position information contained in the first mask, contact trenches extending in a second lateral direction orthogonal to longitudinal axes of the dielectric stripe structures parallel to the first surface.

9. The method of claim 1, further comprising:

forming, using a single lithographic trench mask, cell trenches, field plate trenches and contact trenches extending from the first surface into the semiconductor substrate;

forming the dielectric stripe structures in the cell trenches and from the dielectric stripe structures cell stripes; and

forming field plate stripes in the field plate trenches and contact stripes in the contact trenches.

10. The method of claim 1, further comprising:

providing, before providing the first mask, field plate stripes extending from the first surface into the semiconductor substrate in the first area, wherein longitudinal axes of the field stripe structures are parallel to longitudinal axes of the dielectric stripe structures parallel to the first surface.

11. The method of claim 10, wherein a second width w2 of the field stripe structures orthogonal to the longitudinal axes is greater than a first width w1 of the dielectric stripe structures orthogonal to the longitudinal axes.

12. The method of claim 11, further comprising:

forming a conformal dielectric layer having a thickness greater than half of the first width w1 and smaller than half of the second width w2.

13. The method of claim 1, wherein:

the first mask covers a third area including third stripe and fin sections, the third area spaced from the first area by the second area; and

remnants of the dielectric stripe structures in the third area after forming the recess grooves form third cell insulator structures thicker than a gate dielectric formed in the fin sections.

14. The method of claim 1, further comprising:

providing a source zone directly adjoining the channel/body zones in a first lateral direction defined by longitudinal axes of the dielectric stripe structures parallel to the first surface by introducing impurities through sidewalls of contact trenches formed by using positional information contained in the first mask or a trench mask for forming the dielectric stripe structures.