Thin film transistor and method of manufacturing the same

• US 9,660,094 B2
• Filed: 06/26/2014
• Issued: 05/23/2017
• Est. Priority Date: 01/06/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Eun-Hyun
• Primary Examiner(s): Miyoshi, Jesse Y
• Assistant Examiner(s): Hoang, Tuan A
• Application Number:
  US14/315,712
• Publication Number:
  US 20150194530A1
• Time in Patent Office: 1,062 Days
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, the semiconductor layer overlapping at least a portion of the gate electrode, a plurality of etch stoppers on the semiconductor layer, and a source electrode and a drain electrode spaced apart from each other and disposed on the etch stoppers and the semiconductor layer, wherein a plurality of channel regions are defined in the semiconductor layer by the etch stoppers on the semiconductor layer.

Claims

1. A thin film transistor, comprising:

a gate electrode on a substrate;

a gate insulating layer on the gate electrode;

a semiconductor layer on the gate insulating layer, the semiconductor layer overlapping at least a portion of the gate electrode;

a plurality of etch stoppers on the semiconductor layer, and

a source electrode and a drain electrode, which are spaced apart from each other and disposed on the etch stoppers and the semiconductor layer,

wherein a plurality of channel regions are defined in the semiconductor layer by the plurality of etch stoppers on the semiconductor layer, a width of each channel region being substantially the same as a width of a corresponding one of the etch stoppers, and a space between adjacent ones of the channel regions being substantially the same as a space between corresponding adjacent ones of the etch stoppers, and

wherein portions of the semiconductor layer overlapped by the plurality of etch stoppers are not damaged and portions of the semiconductor layer not overlapped by the plurality of etch stoppers are damaged.

2. The thin film transistor as claimed in claim 1, wherein:

one end portion of each etch stopper is connected to the source electrode such that the one end portion of the etch stopper is between the source electrode and a respective one of the channel regions,

the source electrode directly contacts one portion of the semiconductor layer not covered by an etch stopper,

an opposite end portion of each etch stopper is connected to the drain electrode such that the opposite end portion of each etch stopper is between the drain electrode and the respective one of the channel regions, and

the drain electrode directly contacts an opposite portion of the semiconductor layer not covered by an etch stopper.

3. The thin film transistor as claimed in claim 1, wherein the channel region is a region of the semiconductor layer that is centered under the etch stopper.

4. The thin film transistor as claimed in claim 1, wherein the etch stopper has a width in a range of about 5 μ

m to about 30 μ

m.

5. The thin film transistor as claimed in claim 1, wherein a space between the etch stoppers is in a range of about 5 μ

m to about 30 μ

m.

6. The thin film transistor as claimed in claim 1, wherein the semiconductor layer is an oxide semiconductor layer.

7. The thin film transistor as claimed in claim 6, wherein the oxide semiconductor layer includes at least one selected from the group of zinc (Zn), gallium (Ga), indium (In), and tin (Sn).

8. The thin film transistor as claimed in claim 6, wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), and oxygen (O).

9. A method of manufacturing a thin film transistor, the method comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer covering the gate electrode;

forming a semiconductor layer overlapping at least a portion of the gate electrode;

forming a plurality of etch stoppers on at least a portion of the semiconductor layer; and

forming an electrode-forming material on the substrate and patterning the electrode-forming material to form a source electrode and a drain electrode spaced apart from each other and disposed on the semiconductor layer and the etch stoppers, wherein during the patterning of the electrode-forming material, portions of the semiconductor layer exposed between the plurality of etch stoppers are removed or damaged and portions of the semiconductor layer on which the plurality of etch stoppers are formed are not removed or damaged.

10. The method as claimed in claim 9, wherein:

one end portion of the etch stopper is directly connected to the source electrode such that the one end portion of the etch stopper is between the source electrode and a respective one of the channel regions, and

an opposite end portion of the etch stopper is directly connected to the drain electrode such that the opposite end portion of each etch stopper is between the drain electrode and the respective one of the channel regions.

11. The method as claimed in claim 9, wherein the plurality of etch stoppers define a plurality of channel regions in the portions of the semiconductor layer on which the plurality of etch stoppers are formed, wherein a width of each channel region is substantially the same as a width of a corresponding one of the etch stoppers, and a space between adjacent ones of the channel regions is substantially the same as a space between corresponding adjacent ones of the etch stopper.