Logic chip including embedded magnetic tunnel junctions

• US 9,660,181 B2
• Filed: 03/15/2013
• Issued: 05/23/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Lee, Kevin J., Wang, Yih, Epple, John H., Ghani, Tahir, Steigerwald, Joseph M.
• Primary Examiner(s): Montalvo, Eva Y
• Assistant Examiner(s): Quinto, Kevin
• Application Number:
  US13/994,715
• Publication Number:
  US 20140264668A1
• Time in Patent Office: 1,530 Days
• Field of Search: None
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

Claims

1. An apparatus comprising:

a first magnetic tunnel junction (MTJ) including a first upper MTJ layer, a first lower MTJ layer, and a first tunnel barrier directly contacting a first lower surface of the first upper MTJ layer and a first upper surface of the first lower MTJ layer;

a first spacer; and

a first Inter-Layer Dielectric (ILD) material;

wherein the first upper MTJ layer includes a first upper MTJ layer sidewall and the first lower MTJ layer includes a first lower MTJ sidewall horizontally offset from the first upper MTJ layer sidewall by a first horizontal offset space that defines a first horizontal offset distance;

wherein the first spacer, having a first maximum width no wider than the first horizontal offset distance, directly contacts at least one of the first upper MTJ layer and the first tunnel barrier;

wherein a first horizontal plane, which is parallel to the first lower surface, intersects a first polish stop material that is included between the first MTJ and the first ILD material.

2. The apparatus of claim 1, wherein the first spacer is included entirely within the first horizontal offset space and no portion of the first spacer extends horizontally beyond the first horizontal offset space.

3. The apparatus of claim 1 wherein the first polish stop material directly contacts at least one of the first tunnel barrier and the first lower MTJ layer.

4. The apparatus of claim 1 comprising:

a second MTJ including a second upper MTJ layer, a second lower MTJ layer, and a second tunnel barrier directly contacting a second lower surface of the second upper MTJ layer and a second upper surface of the second lower MTJ layer;

wherein the second upper MTJ layer includes a second upper MTJ layer sidewall and the second lower MTJ layer includes a second lower MTJ sidewall horizontally offset from the second upper MTJ layer sidewall by a second horizontal offset space that defines a second horizontal offset distance; and

a first vertical polish stop sidewall, including the first polish stop material, contacting at least one of the first lower MTJ layer and the first tunnel barrier and a second vertical polish stop sidewall contacting at least one of the second lower MTJ layer and the second tunnel barrier;

wherein (a) the first and second vertical polish stop sidewalls are located between the first and second MTJs and (b) the first horizontal plane intersects the first and second MTJs, and the first and second vertical polish stop sidewalls.

5. The apparatus of claim 1 comprising:

a vertical MTJ layer portion, an additional vertical MTJ layer portion, and a vertical tunnel barrier portion directly contacting the vertical MTJ layer portion and the additional vertical MTJ layer portion;

wherein the vertical MTJ layer portion, the additional vertical MTJ layer portion, and the vertical tunnel barrier portion are all between logic and memory areas included in the apparatus and are all intersected by a first horizontal plane.

6. The apparatus of claim 1, wherein the first spacer directly contacts the first upper MTJ layer and the first tunnel barrier.

7. The apparatus of claim 6 further comprising a first hardmask directly contacting a first upper surface of the first upper MTJ layer and the first spacer.

8. The apparatus of claim 1 including:

a monolithic substrate;

a memory area including the first MTJ; and

a logic area;

wherein the logic area and the memory are both located on the monolithic substrate;

wherein the first horizontal plane intersects the first MTJ, the first ILD material, which is adjacent the first MTJ, and a second ILD material included in the logic area;

wherein the first and second ILD materials are unequal to one another.

9. The apparatus of claim 8, wherein the logic area is included in a processor and the memory is spin torque transfer magnetoresistive random access memory (STT-MRAM).

10. The apparatus of claim 8, wherein:

the first ILD material includes at least one of silicon oxide, silicon oxynitride, porous silicon oxide, fluorinated silicon oxide, carbon-doped oxide, porous carbon-doped oxide, polyimide, polynorbornene, benzocyclobutene, flowable oxide, and polytetrafluoroethylene;

the second ILD material includes an additional at least one of silicon oxide, silicon oxynitride, porous silicon oxide, fluorinated silicon oxide, carbon-doped oxide, porous carbon- doped oxide, polyimide, polynorbornene, benzocyclobutene, flowable oxide, and polytetrafluoroethylene;

the first lower MTJ layer includes sublayers comprising at least two of tantalum;

platinum manganese;

cobalt iron;

Ruthenium (Ru); and

cobalt iron boron; and

the first ILD material includes a first chemical composition and the second ILD material includes a second chemical composition unequal to the first chemical composition.

11. The apparatus of claim 1 comprising:

a monolithic substrate;

a memory area including the first MTJ; and

a logic area;

wherein the first spacer directly contacts the first upper MTJ layer and the first tunnel barrier;

wherein the logic area and the memory are both located on the monolithic substrate;

wherein the first horizontal plane intersects the first MTJ, the first ILD material, which is adjacent the first MTJ, and a second ILD material included in the logic area;

wherein the first and second ILD materials are unequal to one another.

12. The apparatus of claim 11 comprising:

a vertical MTJ layer portion, an additional vertical MTJ layer portion, and a vertical tunnel barrier portion directly contacting the vertical MTJ layer portion and the additional vertical MTJ layer portion;

wherein the vertical MTJ layer portion, the additional vertical MTJ layer portion, and the vertical tunnel barrier portion are all between the logic and memory areas and are all intersected by the first horizontal plane.

13. An apparatus comprising:

a monolithic substrate;

a memory area, comprising a magnetic tunnel junction (MTJ) that includes a tunnel barrier directly contacting lower and upper MTJ layers, located on the substrate; and

a logic area located on the substrate;

wherein a horizontal plane, which is parallel to the tunnel barrier, intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area;

wherein the first ILD material includes a first chemical composition and the second ILD material includes a second chemical composition unequal to the first chemical composition;

wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer sidewall by a horizontal offset space that defines a horizontal offset distance.

14. The apparatus of claim 13 comprising a spacer, having a width equal to the horizontal offset distance, directly contacting the upper MTJ layer and the tunnel barrier.

15. The apparatus of claim 14 further comprising a hardmask directly contacting an upper surface of the upper MTJ layer and the spacer.

16. The apparatus of claim 13 wherein the horizontal plane intersects polish stop material included between the MTJ and the first ILD material.

17. The apparatus of claim 16 wherein the polish stop material directly contacts at least one of the tunnel barrier and the lower MTJ layer.

18. An apparatus comprising:

a first magnetic tunnel junction (MTJ) including a first upper MTJ layer, a first lower MTJ layer, and a first tunnel barrier directly contacting a first lower surface of the first upper MTJ layer and a first upper surface of the first lower MTJ layer;

a first spacer; and

a vertical MTJ layer portion, an additional vertical MTJ layer portion, and a vertical tunnel barrier portion directly contacting the vertical MTJ layer portion and the additional vertical MTJ layer portion;

wherein the first upper MTJ layer includes a first upper MTJ layer sidewall and the first lower MTJ layer includes a first lower MTJ sidewall horizontally offset from the first upper MTJ layer sidewall by a first horizontal offset space that defines a first horizontal offset distance;

wherein the first spacer, having a first maximum width no wider than the first horizontal offset distance, directly contacts at least one of the first upper MTJ layer and the first tunnel barrier;

wherein the vertical MTJ layer portion, the additional vertical MTJ layer portion, and the vertical tunnel barrier portion are all between logic and memory areas included in the apparatus and are all intersected by a first horizontal plane.

19. The apparatus of claim 18 wherein:

the horizontal plane intersects the first MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the first MTJ, and a second ILD material included in the logic area;

wherein the first ILD material includes a first chemical composition and the second ILD material includes a second chemical composition unequal to the first chemical composition.

20. The apparatus of claim 19 wherein the horizontal plane intersects polish stop material included between the first MTJ and the first ILD material.

21. The apparatus of claim 19, wherein the logic area is included in a processor and the memory is spin torque transfer magnetoresistive random access memory (STT-MRAM).

22. An apparatus comprising:

a first magnetic tunnel junction (MTJ) including a first upper MTJ layer, a first lower MTJ layer, and a first tunnel barrier directly contacting a first lower surface of the first upper MTJ layer and a first upper surface of the first lower MTJ layer;

a first spacer; and

a first hardmask directly contacting a first upper surface of the first upper MTJ layer and the first spacer;

wherein the first upper MTJ layer includes a first upper MTJ layer sidewall and the first lower MTJ layer includes a first lower MTJ sidewall horizontally offset from the first upper MTJ layer sidewall by a first horizontal offset space that defines a first horizontal offset distance;

wherein the first spacer, having a first maximum width no wider than the first horizontal offset distance, directly contacts at least one of the first upper MTJ layer and the first tunnel barrier.

23. The apparatus of claim 22 comprising:

a vertical MTJ layer portion, an additional vertical MTJ layer portion, and a vertical tunnel barrier portion directly contacting the vertical MTJ layer portion and the additional vertical MTJ layer portion;

wherein the vertical MTJ layer portion, the additional vertical MTJ layer portion, and the vertical tunnel barrier portion are all between logic and memory areas included in the apparatus and are all intersected by a first horizontal plane.

24. The apparatus of claim 23, wherein the logic area is included in a processor and the memory is spin torque transfer magnetoresistive random access memory (STT-MRAM).