System and method for improving efficiency for quasi-square wave power converters

• US 9,660,531 B1
• Filed: 11/04/2015
• Issued: 05/23/2017
• Est. Priority Date: 11/04/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kar, Monodeep, Bandyopadhyay, Saurav, Morroni, Jeffrey
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US14/932,705
• Publication Number:
  US 20170126122A1
• Time in Patent Office: 566 Days
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A power converter includes a power stage having a switch-node of a switched-mode power supply that is coupled to an input voltage node by a power field-effect transistor (FET) to energize an inductive circuit and is coupled to a ground node by a synchronous rectifier in parallel with the inductive circuit. The power converter also includes a controller coupled to the power stage. The controller controls switching of the power FET and synchronous rectifier in a complimentary manner. The controller switches on the power FET during a first switching cycle. Subsequently, the controller switches on the synchronous rectifier and, in response to a current through the inductive circuit being approximately zero, switches off the synchronous rectifier. Subsequently, the controller switches on the synchronous rectifier again to generate a negative current through the inductive circuit prior to entering a second switching cycle.

Claims

1. A power converter, comprising:

a power stage comprising a switch-node of a switched-mode power supply coupled to an input voltage node by a power field-effect transistor (FET) configured to energize an inductive circuit and coupled to a ground node by a synchronous rectifier in parallel with the inductive circuit; and

a controller coupled to the power stage and to control switching of the power FET and synchronous rectifier in a complimentary manner, wherein the controller is configured to, during a first switching cycle;

switch on the power FET;

subsequently switch on the synchronous rectifier and, in response to a current through the inductive circuit being approximately zero, switch off the synchronous rectifier; and

subsequently switch on the synchronous rectifier again to generate a negative current through the inductive circuit prior to entering a second switching cycle.

2. The power converter of claim 1 wherein a frequency of the switching cycles is based on an output load of the power converter.

3. The power converter of claim 1 wherein after the controller switches off the synchronous rectifier, the switch-node enters an oscillatory state.

4. The power converter of claim 3 wherein the controller is further configured to:

monitor a number of oscillations in the oscillatory state; and

switch on the synchronous rectifier again to generate the negative current prior to entering the second switching cycle in response to the number of oscillations reaching a predetermined threshold based on an output load of the power converter.

5. The power converter of claim 1 wherein the controller is further configured to, during the second switching cycle:

switch on the power FET;

subsequently switch on the synchronous rectifier and, in response to the current through the inductive circuit being approximately zero, switch off the synchronous rectifier; and

subsequently switch on the synchronous rectifier again to generate the negative current through the inductive circuit prior to entering a third switching cycle.

6. The power converter of claim 1 wherein the power FET and the synchronous rectifier comprise transistors, each having a parasitic capacitance between drain and source terminals, and wherein the negative current generated through the inductive circuit reduces losses due to the parasitic capacitance seen by the switch-node.

7. The power converter of claim 1 wherein a duration the power FET is on is based on an output load of the power converter.

8. A controller for a power stage, comprising:

a control circuit for a power field-effect transistor (FET) configured to energize an inductive circuit, the control circuit configured to;

cause the controller to switch on the power FET of the power stage in a first switching cycle;

a control circuit for a synchronous rectifier of the power stage configured to, in the first switching cycle;

subsequently switch on the synchronous rectifier of the power stage causing current through the inductive circuit of the power stage to decrease and, in response to the current through the inductive circuit being approximately zero, switch off the synchronous rectifier; and

subsequently switch on the synchronous rectifier again to generate a negative current through the inductive circuit prior to entering a second switching cycle.

9. The controller for a power stage of claim 8 wherein a frequency of the switching cycles is based on an output load of the power stage.

10. The controller for a power stage of claim 8 wherein after the control circuit for the synchronous rectifier switches off the synchronous rectifier, a switch-node of the power stage enters an oscillatory state.

11. The controller for a power stage of claim 10 wherein the control circuit for the synchronous rectifier is further configured to:

monitor a number of oscillations in the oscillatory state; and

switch on the synchronous rectifier again to generate the negative current prior to entering the second switching cycle in response to the number of oscillations reaching a predetermined threshold based on an output load of the power stage.

12. The controller for a power stage of claim 8 wherein:

the control circuit for the power FET is further configured to, during the second switching cycle, switch on the power FET; and

the control circuit for the synchronous rectifier is further configured to, during the second switching cycle;

subsequently switch on the synchronous rectifier and, in response to the current through the inductive circuit being approximately zero, switch off the synchronous rectifier; and

subsequently switch on the synchronous rectifier again to generate the negative current through the inductive circuit prior to entering a third switching cycle.

13. The controller for a power stage of claim 8 wherein the power FET and the synchronous rectifier comprise transistors, each having a parasitic capacitance between drain and source terminals, and wherein the negative current generated through the inductive circuit reduces losses due to the parasitic capacitance seen by a switch-node of the power stage.

14. The controller for a power stage of claim 8 wherein a duration the power FET is on is based on an output load of the power converter.

15. A method to control a power stage comprising a switch-node of a switched-mode power supply coupled to an input voltage node by a power field-effect transistor (FET) configured to energize an inductive circuit and coupled to a ground node by a synchronous rectifier in parallel with the inductive circuit, the method comprising:

switching on the power FET during a first switching cycle;

subsequently switching on the synchronous rectifier and, in response to a current through the inductive circuit being approximately zero, switching off the synchronous rectifier; and

subsequently switching on the synchronous rectifier again to generate a negative current through the inductive circuit prior to entering a second switching cycle.

16. The method of claim 15 wherein a frequency of the switching cycles is based on an output load of the power stage.

17. The method of claim 15 wherein the switch-node enters an oscillatory state after switching off the synchronous rectifier.

18. The method of claim 17 further comprising:

monitoring a number of oscillations in the oscillatory state; and

switching on the synchronous rectifier again to generate the negative current prior to entering the second switching cycle in response to the number of oscillations reaching a predetermined threshold based on an output load of the power stage.

19. The method of claim 15 further comprising, during the second switching cycle:

switching on the power FET;

subsequently switching on the synchronous rectifier and, in response to the current through the inductive circuit being approximately zero, switching off the synchronous rectifier; and

subsequently switching on the synchronous rectifier again to generate the negative current through the inductive circuit prior to entering a third switching cycle.

20. The method of claim 15 wherein a duration the power FET is on is based on an output load of the power converter.