Dual-edge trigger clock gater

• US 9,660,620 B1
• Filed: 07/22/2016
• Issued: 05/23/2017
• Est. Priority Date: 07/22/2016
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Zyuban, Victor, Kabe, Nimish
• Primary Examiner(s): Zweizig, Jeffrey
• Application Number:
  US15/217,669
• Time in Patent Office: 305 Days
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 2005/00234 using circuits having two logic levels
• CPC Class Codes: H03K 5/01 Shaping pulses discrimination against noise or interference H03K5/125
• CPC Class Codes: H03K 5/134 with field-effect transistors

Abstract

Techniques are disclosed relating to dual-edge triggered clock gater circuitry. In some embodiments, an apparatus includes dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal. In some embodiments, the clock gater circuitry includes first and second storage elements. In some embodiments, the clock gater circuitry includes multiplexer circuitry that selects between outputs of the first and second storage elements to generate the output signal. In some embodiments, the clock gater circuitry includes a third storage element configured to store an indication of which of the first and second storage elements stores a first digital value and which stores an inverse of the first digital value when not gating. In some embodiments, the clock gater circuitry includes a buffering element configured, when gating, to copy data stored in one of the first and second storage elements to the other of the first and second storage elements.

Claims

1. An apparatus, comprising:

dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal, including;

first and second storage elements, wherein the first storage element is controlled by the input clock signal and the second storage element is controlled by an inversion of the input clock signal and wherein, based on a first state of the control signal, one of the first and second storage elements is configured to store a first digital value and the other of the first and second storage elements is configured to store a second digital value that is the inverse of the first digital value;

multiplexer circuitry that is controlled by the input clock signal and is configured to select between outputs of the first and second storage elements to generate the output signal; and

a third storage element configured to store an indication of which of the first and second storage elements stores the first digital value, and provide the first digital value and the inverse of the first digital value to the first and second storage elements based on the first state of the control signal.

2. The apparatus of claim 1, further comprising:

a buffering element configured to, in response to a second state of the control signal, copy data stored in one of the first and second storage elements to the other of the first and second storage elements.

3. The apparatus of claim 2, wherein the buffering element includes a transmission gate that is controlled based on the control signal.

4. The apparatus of claim 1, wherein the third storage element includes cross-coupled inverters.

5. The apparatus of claim 1, wherein the clock gater circuitry is configured to generate the output signal without using feedback from the output signal.

6. The apparatus of claim 1, wherein the first and second storage elements are bi-directional latches and wherein a buffering element is configured to connect an input of the first storage element to an input of the second storage element in response to a second state of the control signal.

7. The apparatus of claim 1, wherein the dual-edge triggered clock gater circuitry is configured to gate a next edge of the input clock signal in response to a second state of the control signal, regardless of whether the next edge is a rising edge or a falling edge.

8. A method, comprising:

generating, by dual-edge trigger clock gater circuitry, an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal;

storing, when not gating the input clock signal, a first digital value in a first storage element and the inverse of the first digital value in a second storage element, wherein the first storage element is controlled by the input clock signal and the second storage element is controlled by an inversion of the input clock signal;

selecting, by multiplexer circuitry based on the input clock signal, between outputs of the first and second storage elements to generate the output signal; and

storing, by a third storage element, an indication of which of the first and second storage elements stores the first digital value, and providing the first digital value and the inverse of the first digital value to the first and second storage elements when not gating the clock signal.

9. The method of claim 8, further comprising:

copying, by a buffering element in response to the control signal indicating to gate the input clock signal, data stored in one of the first and second storage elements to the other of the first and second storage elements.

10. The method of claim 9, wherein the first and second storage elements are bi-directional latches and wherein the copying includes the buffering element connecting an input of the first storage element to an input of the second storage element in response to the control signal indicating to gate the input clock signal.

11. The method of claim 9, wherein the copying, by the buffer element, is performed using a transmission gate that is controlled based on the control signal.

12. The method of claim 8, wherein the storing the indication, by the third storage element, is performed using cross-coupled inverters.

13. The method of claim 8, wherein the generating the output signal is performed without using feedback from the output signal.

14. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, including:

dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal, including;

first and second storage elements, wherein the first storage element is controlled by the input clock signal and the second storage element is controlled by an inversion of the input clock signal, wherein based on a first state of the control signal one of the first and second storage elements is configured to store a first digital value and the other of the first and second storage elements is configured to store a second digital value that is the inverse of the first digital value;

multiplexer circuitry that is controlled by the input clock signal and is configured to select between outputs of the first and second storage elements to generate the output signal; and

a third storage element configured to store an indication of which of the first and second storage elements stores the first digital value, and provide the first digital value and the inverse of the first digital value to the first and second storage elements based on the first state of the control signal.

15. The non-transitory computer readable storage medium of claim 14, wherein the dual-edge triggered clock gater circuitry further includes:

a buffering element configured, in response to a second state of the control signal, to copy data stored in one of the first and second storage elements to the other of the first and second storage elements.

16. The non-transitory computer readable storage medium of claim 15, wherein the design information further specifies that the buffering element includes a transmission gate that is controlled based on the control signal.

17. The non-transitory computer readable storage medium of claim 14, wherein the design information further specifies that the third storage element includes cross-coupled inverters.

18. The non-transitory computer readable storage medium of claim 14, wherein the clock gater circuitry is configured to generate the output signal without using feedback from the output signal.

19. The non-transitory computer readable storage medium of claim 14, wherein the design information further specifies that the first and second storage elements are latches.

20. The non-transitory computer readable storage medium of claim 14, wherein the design information further specifies that the dual-edge triggered clock gater circuitry is configured to gate a next edge of the input clock signal in response to a second state of the control signal, regardless of whether the next edge is a rising edge or a falling edge.