Distributed driver circuitry integrated with GaN power transistors

• US 9,660,639 B2
• Filed: 04/06/2016
• Issued: 05/23/2017
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Original Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Inventors: Mizan, Ahmad, Roberts, John
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US15/091,867
• Publication Number:
  US 20160301408A1
• Time in Patent Office: 412 Days
• Field of Search: None
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/168 in composite switches
• CPC Class Codes: H03K 17/6877 the control circuit comprising active elements different from those used in the output circuit

Abstract

Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

Claims

1. A GaN switching device comprising:

a large area lateral GaN power transistor (GaN FET) arranged as a plurality of sections, and

a distributed driver comprising a plurality of driver elements, each driver element comprising a pull-up driver transistor and a pull-down driver transistor connected in series, wherein the output of each one of the distributed driver elements is selectively connected to drive a respective one of the sections of the large GaN power transistor.

2. The GaN switching device of claim 1, wherein the pull-down driver transistor is distributed as a plurality of pull-down driver transistor elements, each pull-down driver transistor element being arranged for driving a respective section of the GaN power transistor and wherein a single pull-up driver transistor is provided for driving all sections of the GaN power transistor.

3. The GaN switching device of claim 1, wherein both the pull-up driver transistor and pull-down driver transistor are distributed as a plurality of distributed driver elements, each driver element comprising an individual pull-down driver transistor and an individual pull-up driver transistor in series and providing a gate output for driving its respective section of the GaN power transistor.

4. The GaN switching device of claim 1, wherein the plurality of sections of the GaN FET and the plurality of driver elements are arranged to provide a layout wherein each one of the distributed driver elements is placed in close physical proximity to the respective one of the sections of the large GaN FET that it drives.

5. The GaN switching device of claim 1, wherein each one of the driver elements is placed in close physical proximity to the respective one of the sections of the large GaN power switch, and wherein routing and sizing of respective interconnect tracks connecting the distributed driver elements and respective sections of GaN switch are selected to minimize loop inductance.

6. The device of claim 1, wherein the gate output track connection of the driver element which drives a section of the gate of the large GaN power switch and the return track connection to the source of the pull-down driver transistor of the driver element are magnetically mirrored so as to reduce the loop inductance.

7. The device of claim 1, wherein the routing and sizing of interconnect tracks for the gate output and return between each driver element and respective sections of the GaN power switch are arranged to reduce the loop inductance.

8. The device of claim 7, wherein said tracks comprise two layer tracks arranged in parallel.

9. The device of claim 7, wherein said tracks comprise three parallel tracks wherein a signal line is encompassed by drive lines, above and below the signal line.

10. A GaN switching device comprising:

a substrate;

an enhancement mode (E-Mode) GaN switch and an integrated GaN driver formed on the substrate;

the E-Mode GaN switch comprising a large area lateral GaN transistor switch D3 having an active area that is partitioned into a plurality of sections (D3₁ to D3_n);

the integrated GaN driver being integrated monolithically on the substrate adjacent the active area of GaN transistor D3; and

the integrated GaN driver being distributed as a corresponding plurality of driver elements, each driver element being located on the substrate in close proximity to a respective one of the plurality of sections of D3 and coupled to the respective section of D3 by low inductance interconnects.

11. A GaN switching device according to claim 10, wherein each driver element comprises a first, pull-up E-Mode GaN driver transistor D1 and a second, pull-down E-Mode GaN driver transistor D2;

the drain of D1 being coupled to Vcc, and the source of D1 being coupled to the drain of D2 at node N, which is coupled to the gate of the respective section of D3, and an internal source-sense connection closely coupling the source of the respective section of D3 and the source of D2, such that the first transistor D1 delivers a drive voltage to the gate of the respective section of the GaN transistor switch D3, and the second transistor D2 clamps the gate of the respective section the GaN transistor switch D3 by means of the internal source-sense connection SS_internal;

inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D1 and D2 of each driver element and optionally to the gates of each section of D3, and

an external source-sense connection SS_external for coupling to the pre-driver.

12. The device of claim 10, wherein each section D3_n of D3 has a respective individual driver element comprising a pull-up driver element D1_n, and a pull-down driver element D2_n.

13. The device of claim 10, wherein each section D3_n of D3 is coupled to a respective individual pull-down driver element D1_n, and wherein a single pull-up driver element D2 is coupled to the plurality of sections of D3.

14. The device of claim 11, wherein each section D3_n of D3 has a respective individual driver element comprising a pull-up driver D1_n and a pull-down driver D2_n.

15. The device of claim 11, wherein each section D3_n of D3 is coupled to a respective individual pull-down driver element D1_n, and wherein a single pull-up driver element D2 is coupled to a plurality of sections of D3.