Method and circuit for parasitic capacitance cancellation for self capacitance sensing

• US 9,665,215 B2
• Filed: 03/29/2013
• Issued: 05/30/2017
• Est. Priority Date: 03/29/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Asia Pacific Pte Limited (STMicroelectronics NV)
• Inventors: Guedon, Yannick, Tan, Sze-Kwang
• Primary Examiner(s): Boyd, Jonathan
• Application Number:
  US13/853,887
• Publication Number:
  US 20140292705A1
• Time in Patent Office: 1,523 Days
• Field of Search: 345174, 345175, 345173, 345 98, 178 1806
• CPC Class Codes: G06F 3/04182 Filtering of noise external to the device and not generated by digitiser components
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

Apparatus and methods to measure capacitance changes for a touch-sensitive capacitive matrix are described. Charge-removal circuits and measurement techniques may be employed to cancel deleterious effects of parasitic capacitances in the touch-sensitive capacitive matrix. Capacitively switching a supply during timed charge removal may be used to cancel unwanted effects due to clock jitter. The apparatus and methods can improve signal-to-noise characteristics, sensitivity, and/or dynamic range for capacitive measurements relating to touch-sensitive capacitive devices.

Claims

1. An electronic device comprising:

a touch-sensitive capacitive matrix having a plurality of force channels and a plurality of sense channels that are used for capacitive measurements to detect touch of the touch-sensitive capacitive matrix;

an output amplifier configured to be coupled to and decoupled from at least one sense channel of the plurality of sense channels;

wherein said at least one sense channel includes a parasitic capacitance; and

a charge removal circuit including a discharge circuit configured to sink a constant magnitude current from the parasitic capacitance at said at least one sense channel for a duration of time so as to cancel a parasitic charge stored by said parasitic capacitance at said at least one sense channel.

2. The electronic device of claim 1, wherein the touch-sensitive capacitive matrix is incorporated in a display screen to form a touch screen.

3. The electronic device of claim 1, wherein the output amplifier is configured to provide an output signal representative of a change in capacitance due to a touching of the touch-sensitive capacitive matrix.

4. The electronic device of claim 1, wherein the output amplifier comprises:

a non-inverting input coupled to a first reference voltage;

an inverting input configured to receive a signal from the at least one sense channel; and

a first capacitor connected between the inverting input and an output of the output amplifier.

5. The electronic device of claim 1, wherein the charge removal circuit comprises a switch for connecting and disconnecting a transistor current source to and from the at least one sense channel for said duration of time.

6. The electronic device of claim 1, wherein the charge removal circuit comprises a current mirror including a transistor current source, wherein a first transistor of the current mirror is shared by the transistor current source for each of the plurality of sense channels to remove the parasitic charge from parasitic capacitances associated with more than one sense channel.

7. The electronic device of claim 6, further comprising a switch configured to connect said transistor current source of the current mirror with a sense channel of the more than one sense channels.

8. The electronic device of claim 6, further comprising:

a second transistor coupled between the first transistor and a first supply; and

a supply amplifier having an output coupled to a gate node of the second transistor.

9. The electronic device of claim 8, wherein an inverting input of the supply amplifier is coupled to a node between the second transistor and the first supply.

10. The electronic device of claim 1, wherein the charge removal circuit comprises:

a current mirror having a first transistor and a transistor current source, wherein a conduction terminal of the first transistor of the current mirror is coupled to receive a switch current output from a switched-capacitive supply circuit, said constant magnitude current derived from the switch current; and

a first switch coupled between the transistor current source and the at least one sense channel.

11. The electronic device of claim 10, wherein the switched-capacitive supply circuit comprises:

a second switch;

a third switch coupled in series with and between the second switch and the first transistor; and

a switched capacitor coupled to a node between the second switch and the third switch.

12. The electronic device of claim 11, wherein the second switch and third switch are respectively driven by a first pulse signal and a second pulse signal of opposite phase.

13. The electronic device of claim 12, wherein the second and third switches are driven at a same clock frequency and the first switch is controlled to be in an on state for a time duration determined by the same clock frequency.

14. A method for measuring capacitance at a sense channel of an electronic device wherein a parasitic capacitance is associated with the sense channel, the method comprising:

applying a first voltage to the sense channel;

executing a calibration measurement to determine a value of the parasitic capacitance;

determining a value of a compensating charge based at least in part on the determined value of the parasitic capacitance and the applied first voltage; and

connecting a discharge circuit to the sense channel for a duration of time to sink a constant magnitude current from the parasitic capacitance and generate said compensating charge which cancels a parasitic charge stored by the parasitic capacitance at said sense channel.

15. The method of claim 14, wherein the sense channel is a sense channel of a touch-sensitive capacitive matrix and the measured capacitance is a capacitance induced by an object touching the touch-sensitive capacitive matrix.

16. The method of claim 14, further comprising determining a value for the duration of time based upon the determined value of the compensating charge and a value of the constant magnitude current.

17. The method of claim 14, wherein connecting comprises:

applying the constant magnitude current to the sense channel for a selected number of cycles of an internal clock signal of the electronic device that is equal to said duration of time; and

capacitively switching a supply voltage to the current source at a same frequency as the internal clock signal.

18. The method of claim 14, further comprising:

applying a second voltage to the sense channel; and

connecting an amplifier to the sense channel to amplify an output from the sense channel and provide an output voltage representative of sensed capacitance by the sense channel.

19. The method of claim 18, wherein the acts of connecting a current source, applying a second voltage, and connecting an amplifier are initiated at substantially the same time.

20. The method of claim 18, wherein connecting a current source occurs during a time interval after the act of applying a first voltage has concluded and before the acts of applying a second voltage, and connecting an amplifier are initiated.

21. An electronic device comprising:

a sense channel configured to be coupled to a touch-sensitive capacitive matrix, wherein the sense channel has a parasitic capacitance;

an output amplifier having an input selectively connected to the sense channel and configured to convert a sensed capacitance to an output voltage; and

a discharge circuit selectively connected to the sense channel and configured to sink a constant magnitude current from the parasitic capacitance at the sense channel for a time period having a selected length so as to discharge a parasitic charge stored by said parasitic capacitance.

22. The electronic device of claim 21, wherein the discharge circuit comprises a switch for connecting and disconnecting a transistor current source to and from the sense channel for said duration of time.

23. The electronic device of claim 21, wherein the discharge circuit comprises a current mirror including a transistor current source, wherein a first transistor of the current mirror is shared by the transistor current source for each sense channel of a plurality of sense channels to remove the parasitic charge from parasitic capacitances associated with more than one sense channel.

24. The electronic device of claim 23, further comprising a switch configured to connect said transistor current source of the current mirror with the sense channel.

25. The electronic device of claim 23, further comprising:

a second transistor coupled between the first transistor and a first supply; and

a supply amplifier having an output coupled to a gate node of the second transistor.

26. The electronic device of claim 25, wherein an inverting input of the supply amplifier is coupled to a node between the second transistor and the first supply.

27. The electronic device of claim 21, wherein the discharge circuit comprises:

a current mirror having a first transistor and a transistor current source, wherein a conduction terminal of the first transistor of the current mirror is coupled to receive a switch current output from a switched-capacitive supply circuit, said constant magnitude current derived from the switch current; and

a first switch coupled between the transistor current source and the at least one sense channel.

28. The electronic device of claim 27, wherein the switched-capacitive supply circuit comprises:

a second switch;

a third switch coupled in series with and between the second switch and the first transistor; and

a switched capacitor coupled to a node between the second switch and the third switch.

29. The electronic device of claim 28, wherein the second switch and third switch are respectively driven by a first pulse signal and a second pulse signal of opposite phase.

30. The electronic device of claim 29, wherein the second and third switches are driven at a same clock frequency and the first switch is controlled to be in an on state for a time duration determined by the same clock frequency.