Hardware task manager

• US 9,665,397 B2
• Filed: 07/15/2014
• Issued: 05/30/2017
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Cornami, Inc.
• Original Assignee: Cornami, Inc.
• Inventors: Scheuermann, W. James, Hogenauer, Eugene B.
• Primary Examiner(s): DONAGHUE, LARRY D
• Application Number:
  US14/331,741
• Publication Number:
  US 20140331231A1
• Time in Patent Office: 1,050 Days
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/17331 Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A hardware task manager for an adaptive computing system. The adaptive computing system includes a plurality of computing nodes including an execution unit configured to execute tasks. An interconnection network is operatively coupled to the plurality of computing nodes to provide interconnections among the plurality of computing nodes. The hardware task manager manages execution of the tasks by the execution unit.

Claims

1. An integrated circuit comprising:

a plurality of computing nodes, at least one of the plurality computing nodes comprising an execution unit configured to execute tasks;

an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes; and

a hardware task manager in at least one of the plurality of computing nodes, the hardware task manager managing execution of tasks by the execution unit.

2. The integrated circuit of claim 1, wherein the plurality of computing nodes comprise a plurality of heterogeneous computing nodes.

3. The integrated circuit of claim 1, wherein the hardware task manager is configured to process the tasks in a task list.

4. The integrated circuit of claim 1, wherein the hardware task manager is configured to maintain a state information table configured to provide the state of each task.

5. The integrated circuit of claim 1, wherein the hardware task manager is configured to provide a ports count for a created task to indicate the availability of input ports and output ports to the created task.

6. The integrated circuit of claim 5, wherein the availability is based on a predetermined amount of available data.

7. The integrated circuit of claim 1, wherein the at least one computing node further comprises a node wrapper, the node wrapper interfacing the execution unit to the interconnection network.

8. An integrated circuit comprising:

a plurality of computing nodes, at least one computing node comprising an execution unit configured to execute tasks;

an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes;

a hardware task manager in at least one of the plurality of computing nodes; and

a ready-to-run queue in communication with the hardware task manager and configured to identify tasks that are ready to be executed by the execution unit.

9. The integrated circuit of claim 8, wherein a task is identified as one of a plurality of states, the plurality of states selected from the group consisting of:

a suspend state identifying tasks created by a control node;

an idle state identifying tasks that are not ready for execution;

a ready state identifying tasks that are ready for execution; and

a run state identifying tasks that are being executed by the execution unit.

10. The integrated circuit of claim 8, wherein a task is added to the ready-to-run queue when a task is identified as the ready state by the hardware task manager.

11. The integrated circuit of claim 8, wherein the hardware task manager is configured to communicate with the execution unit to execute a task when the execution unit is idle and the task is the next task in the ready-to-run queue.

12. The integrated circuit of claim 8, wherein the hardware task manager is further configured to determine a status of at least one buffer associated with a task and identify a task as ready to run based on the status of the at least one buffer.

13. The integrated circuit of claim 12, wherein the at least one buffer comprises at least one input buffer and at least one output buffer.

14. The integrated circuit of claim 8, wherein the hardware task manager is configured to identify the task as ready to run when the at least one input buffer and the at least one output buffer associated with the task are available.

15. The integrated circuit of claim 14, wherein the hardware task manager is configured to determine the status of the at least one buffer using a buffer counter.

16. The integrated circuit of claim 15, wherein the buffer counter is changed when a unit of data is placed into at least one buffer and when a unit of data is removed from the at least one buffer.

17. The integrated circuit of claim 8, wherein each task is associated with a task identifier, and wherein the ready-to-run queue is configured to identify tasks in the ready-to-run queue with the task identifier.