Mixed three-dimensional printed memory

• US 9,666,237 B2
• Filed: 03/03/2015
• Issued: 05/30/2017
• Est. Priority Date: 04/14/2014
• Status: Expired due to Fees

• Current Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Original Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Zarroli, Michael
• Application Number:
  US14/636,353
• Publication Number:
  US 20150294692A1
• Time in Patent Office: 819 Days
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/367 Gate dielectric programmed, e.g. different thickness
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM

Abstract

The present invention discloses a mixed three-dimensional printed memory (3D-P). The slow contents (e.g., digital books, digital maps, music, movies, and/or videos) are stored in large memory blocks and/or large memory arrays, whereas the fast contents (e.g., operating systems, software, and/or games) are stored in small memory blocks and/or small memory arrays.

Claims

1. A mixed three-dimensional printed memory (3D-P) comprising a plurality of memory blocks including a 3D-P block, wherein:

said 3D-P block comprises a plurality of vertically stacked memory levels including a topmost memory level, wherein said topmost memory level is the topmost memory level among all of said memory levels;

said 3D-P block comprises a first memory array in said topmost memory level;

said 3D-P block further comprises at least second and third memory arrays in a memory level below said topmost memory level, wherein said second and third memory arrays are located on a same memory level and do not share any address-select line;

said first memory array fully covers both said second and third memory arrays.

2. The memory according to claim 1, wherein said first memory array stores digital books.

3. The memory according to claim 1, wherein said first memory array stores digital maps.

4. The memory according to claim 1, wherein said first memory array stores music.

5. The memory according to claim 1, wherein said first memory array stores movies.

6. The memory according to claim 1, wherein said first memory array stores videos.

7. The memory according to claim 1, wherein said second or third memory array stores operating system.

8. The memory according to claim 1, wherein said second or third memory array stores software.

9. The memory according to claim 1, wherein said second or third memory array stores games.