Data storage device with temperature compensation and operating method thereof

• US 9,666,249 B1
• Filed: 06/21/2016
• Issued: 05/30/2017
• Est. Priority Date: 02/24/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Park, Sang Hyun
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/188,732
• Time in Patent Office: 343 Days
• Field of Search: 365211
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage device includes a nonvolatile memory device including a memory cell region which is divided into a first region and a second region; and a controller configured to control a program operation of the nonvolatile memory device according to a write request of an external device, wherein the controller provides a temperature compensation off command to the nonvolatile memory device before providing data, a program command for commanding program of the data and an address of the first region to the nonvolatile memory device, and wherein, while programming the data in a memory cell corresponding to the address of the first region according to the program command for commanding program of the data, the nonvolatile memory device omits a temperature compensation operation of changing a program verify operation to be applied to the memory cell, according to a temperature variation.

Claims

1. A data storage device comprising:

a nonvolatile memory device including a first region including a buffer region and a second region including a data region; and

a controller suitable for controlling the nonvolatile memory device to perform a buffer program operation by storing write data in the first region in response to a program command from a host, report completion of the buffer program operation upon completion of the buffer program operation, and perform a main program operation by moving the write data from the first region to the second region,

wherein the controller controls the nonvolatile memory device to perform a temperature compensation operation only for the second region.

2. The data storage device according to claim 1, wherein the controller controls the nonvolatile memory device to perform the buffer program operation without the temperature compensation operation.

3. The data storage device according to claim 1,

wherein, during the main program operation, the controller provides a read command and an address of the first region to the nonvolatile memory device,

wherein, during the main program operation, the nonvolatile memory device provides the controller with the write data read out from a memory cell corresponding to the address of the first region according to the read command,

wherein, during the main program operation, the controller provides the nonvolatile memory device with the read-out write data, a program command for commanding program of the read-out write data and an address of the second region, and

wherein, during the main program operation, the nonvolatile memory device programs the read-out write data in a memory cell corresponding to the address of the second region according to the program command for commanding program of the read-out data.

4. The data storage device according to claim 1, wherein the nonvolatile memory device comprises:

a temperature sensor suitable for measuring an internal temperature; and

a control logic suitable for controlling an operation for the memory cell region according to a command provided from the controller,

wherein the control logic disables the temperature sensor during the buffer program operation.

5. The data storage device according to claim 4, wherein, when it is determined that a temperature measured through the temperature sensor is lower than a reference voltage, the control logic performs the temperature compensation operation by changing the program verify voltage to a cold program verify voltage having a voltage level lower than a normal program verify voltage and applying the cold program verify voltage.

6. The data storage device according to claim 4, wherein, when it is determined that a temperature measured through the temperature sensor is higher than the reference voltage, the control logic performs the temperature compensation operation by changing the program verify voltage to a hot program verify voltage having a voltage level higher than the normal program verify voltage and applying the hot program verify voltage.

7. The data storage device according to claim 1, wherein memory cell schemes between the first region and the second region are different from each other.

8. The data storage device according to claim 1, wherein storage capacity per memory cell of the first region is smaller than that of the second region.

9. The method according to claim 1, wherein the memory cells in the first region are SLCs and the memory cells in the second region are MLCs.

10. The method according to claim 1, wherein the memory cells in the first region are 2-bit cells and the memory cells in the second region are 3-bit cells.

11. A method for operating a data storage device including a first region including a buffer region and a second region including a data region, the method comprising:

performing a buffer program operation by storing write data in the first region in response to a program command from a host;

reporting completion of a program operation with the write data to the host upon completion of the buffer program operation; and

performing a main program operation by moving the write data from the first region to the second region,

wherein a temperature compensation operation is performed only to the second region.

12. The method according to claim 11, wherein the temperature compensation operation is omitted during the buffer program operation.

13. The method according to claim 11, the performing the main program operation comprises:

reading out the write data from the first region; and

programming the read-out write data in the second region.

14. The method according to claim 11, wherein performing the buffer program operation includes disabling a temperature sensor for the temperature compensation operation.

15. The method according to claim 11, wherein, when it is determined that a temperature measured through the temperature sensor is lower than a reference voltage, the temperature compensation operation is performed by changing the program verify voltage to a program verify voltage having a voltage level lower than a normal program verify voltage and applying the changed program verify voltage.

16. The method according to claim 11, wherein, when it is determined that a temperature measured through the temperature sensor is higher than the reference voltage, the temperature compensation operation is performed by changing the program verify voltage to a program verify voltage having a voltage level higher than the normal program verify voltage and applying the changed program verify voltage.

17. The method according to claim 11, wherein memory cell schemes between the first region and the second region are different from each other.

18. The method according to claim 11, wherein the storage capacity of the memory cells in the first region is smaller than the storage capacity of the memory cells in the second region.

19. The method according to claim 11, wherein the memory cells in the first region are SLCs and the memory cells in the second region are MLCs.