Memory signal buffers and modules supporting variable access granularity

• US 9,666,250 B2
• Filed: 01/19/2016
• Issued: 05/30/2017
• Est. Priority Date: 08/05/2011
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Shaeffer, Ian
• Primary Examiner(s): Shyu, Jing-Yih
• Application Number:
  US15/000,394
• Publication Number:
  US 20160203848A1
• Time in Patent Office: 497 Days
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described are memory modules that include a configurable signal buffer that manages communication between memory devices and a memory controller. The buffer can be configured to support threading to reduce access granularity, the frequency of row-activation, or both. The buffer can translate controller commands to access information of a specified granularity into subcommands seeking to access information of reduced granularity. The reduced-granularity information can then be combined, as by concatenation, and conveyed to the memory controller as information of the specified granularity.

Claims

1. A memory module comprising:

a first memory device group, including at least one memory device;

a second memory device group, separate from the first memory device group and comprising at least one memory device; and

a signal buffer having;

a first memory command interface coupled to the first memory device group;

a second memory command interface coupled to the second memory device group;

a module command interface to receive module commands, including a module read command; and

logic to send a first memory-device read command and a second memory-device read command to the first memory device group via the first memory command interface responsive to the module read command;

wherein the logic;

receives a first set of data responsive to the first memory-device read command;

receives a second set of data responsive to the second memory-device read command; and

combines the first set of data with the second set of data.

2. The memory module of claim 1, wherein the logic conveys the combined first set of data and second set of data from the signal buffer.

3. The memory module of claim 1, the signal buffer to receive an activate command specifying a memory address and store at least a portion of the memory address in a look-up table.

4. The memory module of claim 3, the logic to look up the at least a portion of the memory address from the look-up table responsive to the module read command.

5. The memory module of claim 4, wherein the at least a portion of the memory address specifies the first memory device group.

6. A signal buffer comprising:

a primary command interface to receive a module-access command;

a first secondary command interface to issue first memory-access commands;

a second secondary command interface to issue second memory-access commands; and

logic coupled between the primary command interface and each of the first and second secondary command interfaces, the logic to generate, from the module-access command, a sequence of memory-device commands, and to convey the sequence of memory-device commands to one of the first and second secondary command interfaces;

wherein the logic directs the memory-device commands in the sequence of memory-device commands to different column addresses.

7. The signal buffer of claim 6, wherein the logic directs the memory-device commands in the sequence of memory-device command to a common row address.

8. The signal buffer of claim 6, the logic to receive a set of data responsive to each memory-device command in the sequence of memory-device commands, and to reorder the data in the sets of data.

9. The signal buffer of claim 6, further comprising:

a primary data interface to communicate primary data of a primary-data width; and

first and second secondary data interfaces to communicate secondary data of a secondary-data width less than the primary-data width;

wherein the module-access command requests first read data of the primary-data width and each of the memory-device commands requests second read that of the secondary-data width.

10. The signal buffer of claim 9, wherein the secondary-data width is half the primary-data width.

11. A method for providing wide read data from a memory module,

the method comprising:

receiving, at the memory module, a module read command specifying a row address;

generating, from the module read command, a sequence of memory-device read commands specifying different column addresses;

issuing the sequence of memory-device read commands to obtain sets of narrow read data;

combining the sets of narrow read data; and

communicating the sets of narrow read data as at least part of the wide read data from the memory module.

12. The method of claim 11, further comprising:

receiving, at the memory module, an activate command specifying a memory address, including the row address, before receiving the module read command; and

storing at least part of the memory address in a look-up table.

13. The method of claim 12, further comprising looking up the at least part of the memory address from the look-up table responsive to the module read command.

14. The method of claim 13, wherein the at least part of the memory address specifies a rank group of memory devices, the method further comprising directing the sequence of memory-device read commands to the rank group of memory devices.

15. The method of claim 14, further comprising:

receiving, at the memory module, an precharge command specifying the memory address after receiving the module read command;

looking up the at least part of the memory address from the look-up table responsive to the precharge command; and

precharging memory cells in the rank group of memory devices.

16. The method of claim 11, further comprising:

receiving, at the memory module, a second module read command specifying a second row address;

generating, from the second module read command, a second sequence of memory-device read commands specifying different second column addresses;

issuing the second sequence of memory-device read commands to obtain second sets of narrow read data;

combining the second sets of narrow read data; and

communicating the second sets of narrow read data as at least part of the wide read data from the memory module.

17. The method of claim 16, further comprising communicating the first-mentioned and second sets of narrow read data concurrently.

18. The method of claim 16, further comprising communicating the first-mentioned and second sets of narrow read data sequentially.

19. The method of claim 16, further comprising interleaving the first-mentioned set of narrow read data with the second set of narrow read data.