System and method for MRAM having controlled averagable and isolatable voltage reference

• US 9,666,274 B2
• Filed: 08/23/2016
• Issued: 05/30/2017
• Est. Priority Date: 10/21/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Taehyun, Kim, Jung Pill
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US15/244,456
• Publication Number:
  US 20160358649A1
• Time in Patent Office: 280 Days
• Field of Search: 365 48, 365 66, 365 78, 365 80- 93, 365100, 365130, 365131, 365148, 365158, 365163, 365171, 365173, 3652255, 3652435, 257 2- 5, 257296, 257E31047, 257E21665, 438 29, 438 95, 438 96, 438166, 438259, 438365, 438482, 438486, 438597
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

Claims

1. A Non-Volatile Resistive bitcell array memory comprising:

means for generating a first reference voltage;

means for generating a second reference voltage;

means for providing a first sensing reference and a second sensing reference, including means for selectively combining the first reference voltage and the second reference voltage into a common voltage and for selectively providing the common voltage as the first sensing reference, and means for selectively providing the first reference voltage as the first sensing reference;

means for sensing a voltage of a first array of bitcells relative to the first sensing reference; and

means for sensing a voltage of a second array of bitcells relative to the second sensing reference.

2. The memory of claim 1, wherein the means for providing the first sensing reference and the second sensing reference further includes means for selectively providing the second reference voltage as the second sensing reference.

3. The memory of claim 1, wherein the means for providing the first sensing reference and the second sensing reference further includes means for selectively providing the first reference voltage as the second sensing reference.