Three-dimensional one-time-programmable memory comprising off-die address/data-translator
First Claim
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1. A discrete three-dimensional one-time-programmable memory (3D-OTP), comprising:
- a 3D-array die comprising at least a 3D-OTP array, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells;
a peripheral-circuit die comprising at least an off-die A/D-translator of said 3D-OTP array, wherein said off-die A/D-translator converts at least an address and/or data between logic and physical spaces;
means for coupling said 3D-array die and said peripheral-circuit die;
wherein the number of back-end-of-line (BEOL) levels in said 3D-array die is at least twice as much as the number of interconnect levels in said peripheral-circuit die;
said off-die A/D-translator is absent from said 3D-array die; and
, said 3D-array die and said peripheral-circuit die are separate dice.
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Abstract
The present invention discloses a three-dimensional one-time-programmable memory (3D-OTP) comprising an off-die address/data-translator (A/D-translator). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an A/D-translator of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The A/D-translator converts at least an address and/or data between logic and physical spaces.
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20 Claims
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1. A discrete three-dimensional one-time-programmable memory (3D-OTP), comprising:
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a 3D-array die comprising at least a 3D-OTP array, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells; a peripheral-circuit die comprising at least an off-die A/D-translator of said 3D-OTP array, wherein said off-die A/D-translator converts at least an address and/or data between logic and physical spaces; means for coupling said 3D-array die and said peripheral-circuit die; wherein the number of back-end-of-line (BEOL) levels in said 3D-array die is at least twice as much as the number of interconnect levels in said peripheral-circuit die;
said off-die A/D-translator is absent from said 3D-array die; and
, said 3D-array die and said peripheral-circuit die are separate dice. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A discrete three-dimensional one-time-programmable memory (3D-OTP), comprising:
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a 3D-array die comprising at least a 3D-OTP array, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells; a peripheral-circuit die comprising at least an off-die A/D-translator of said 3D-OTP array, wherein said off-die A/D-translator converts at least an address and/or data between logic and physical spaces; means for coupling said 3D-array die and said peripheral-circuit die; wherein the number of interconnect levels in said peripheral-circuit die is more than the number of interconnect levels in said 3D-array die, but substantially less than the number of back-end-of-line (BEOL) levels in said 3D-array die;
said off-die A/D-translator is absent from said 3D-array die; and
, said 3D-array die and said peripheral-circuit die are separate dice. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A discrete three-dimensional one-time-programmable memory (3D-OTP), comprising:
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a 3D-array die comprising at least a 3D-OTP array and an in-die peripheral-circuit component, wherein said 3D-OTP array comprises a plurality of vertically stacked 3D-OTP cells; a peripheral-circuit die comprising at least an off-die A/D-translator of said 3D-OTP array, wherein said off-die A/D-translator converts at least an address and/or data between logic and physical spaces; means for coupling said 3D-array die and said peripheral-circuit die; wherein said in-die peripheral-circuit component and said off-die A/D-translator comprise different interconnect materials;
said off-die A/D-translator is absent from said 3D-array die; and
, said 3D-array die and said peripheral-circuit die are separate dice. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification