Method of forming semiconductor device

• US 9,666,491 B1
• Filed: 06/16/2016
• Issued: 05/30/2017
• Est. Priority Date: 06/16/2016
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Zhou, Zhibiao, Chen, Ding-Lung
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Yi, Changhyun
• Application Number:
  US15/185,007
• Time in Patent Office: 348 Days
• Field of Search: 438667
• CPC Class Codes: H01L 21/428 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8256 the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252 and H01L21/8254 H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365

Abstract

A method of forming a semiconductor device includes following steps. Firstly, a first transistor is formed on a first surface of a substrate. Next, a thinning process is performed on the second surface of the substrate which is opposite to the first surface, to form a third surface. Then, a second transistor is formed on the third surface, in which the second transistor and the first transistor are electrically connected to each other through a through-silicon via penetrating through the first surface and the third surface.

Claims

1. A method of forming a semiconductor device, comprising:

providing a substrate having a first surface and a second surface opposite to the first surface;

forming a first transistor on the first surface of the substrate;

performing a thinning process on the second surface of the substrate to form a third surface;

forming a first insulating layer on the third surface of the substrate;

forming an oxide semiconductor (OS) layer on the first insulating layer;

forming a source and a drain on the OS layer;

forming a second insulating layer covering the source, the drain and the OS layer;

forming a first gate electrode on the OS layer between the source and the drain, wherein the OS layer, the second insulating layer, the source, the drain and the first gate electrode together form a second transistor on the third surface;

performing a first annealing process to form a seal layer covering the second transistor;

forming a second gate electrode on the first insulating layer; and

performing a second annealing process to form a third insulating layer covering the second gate electrode.

2. The method of forming a semiconductor device according to claim 1, wherein the seal layer comprises less than 1% hydrogen after the first annealing process.

3. The method of forming a semiconductor device according to claim 1, further comprising a capacitor on the second transistor.

4. The method of forming a semiconductor device according to claim 1, wherein the second transistor and capacitor are formed in a first dielectric layer on the third surface of the substrate, and the first transistor is formed in a second dielectric layer on the first surface of the substrate.

5. The method of forming a semiconductor device according to claim 1, further comprising:

forming a via penetrated through the third surface and the first surface of the substrate, wherein the via is electrically connected the second transistor and the first transistor.

6. The method of forming a semiconductor device according to claim 1, wherein the first annealing process and the second annealing process comprises a rapid thermal process or a laser spike annealing process.

7. The method of forming a semiconductor device according to claim 1, wherein the first insulating layer is formed through a third annealing process.

8. The method of forming a semiconductor device according to claim 7, wherein the third annealing process comprises a rapid thermal process or a laser spike annealing process.

9. A method of forming a semiconductor device, comprising:

providing a substrate having a first surface and a second surface opposite to the first surface;

forming a first transistor on the first surface of the substrate;

performing a thinning process on the second surface of the substrate to form a third surface;

forming a first insulating layer on the third surface of the substrate;

forming an oxide semiconductor (OS) layer on the first insulating layer;

after the forming of the OS layer, performing an oxidation treatment;

forming a source and a drain on the OS layer;

forming a second insulating layer covering the source, the drain and the OS layer;

forming a first gate electrode on the OS layer between the source and the drain, wherein the OS layer, the second insulating layer, the source, the drain and the first gate electrode together form a second transistor on the third surface; and

performing a first annealing process to form a seal layer covering the second transistor.