Substrate for mounting a chip and chip package using the substrate

• US 9,666,558 B2
• Filed: 06/29/2015
• Issued: 05/30/2017
• Est. Priority Date: 06/29/2015
• Status: Active Grant

• Current Assignee: Point Engineering Co. Ltd.
• Original Assignee: Point Engineering Co. Ltd.
• Inventors: Ahn, Bum Mo, Park, Seung Ho, Nam, Ki Myung
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US14/753,807
• Publication Number:
  US 20160379957A1
• Time in Patent Office: 701 Days
• Field of Search: 257737, 257773
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 25/065 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Abstract

Disclosed is a chip-mounting substrate. The chip-mounting substrate includes a plurality of conductive portions configured to apply voltages to at least two or more chips to be mounted, a plurality of insulation portions formed between the conductive portions and configured to electrically isolate the conductive portions, and a cavity formed in a region which includes at least three or more of the conductive portions and at least two or more of the insulation portions and depressed inward to form a space in which the chips are mounted.

Claims

1. A chip-mounting substrate, comprising:

a plurality of conductive portions configured to apply voltages to at least two or more chips to be mounted;

a plurality of insulation portions formed between the conductive portions and configured to electrically isolate the conductive portions;

a cavity formed in a region which includes at least three or more of the conductive portions and at least two or more of the insulation portions and depressed inward to form a space in which the chips are mounted; and

through-holes located on cutting lines of the chip-mounting substrate so as to penetrate and divide the insulation portions, wherein the cutting lines are lines along which the chip-mounting substrate is diced into unit chip-mounting substrates.

2. The chip-mounting substrate of claim 1, wherein the conductive portions which adjoin each other with each of the insulation portions interposed therebetween are applied with voltages of opposite polarities.

3. The chip-mounting substrate of claim 2, wherein the chips mounted on a common one of the conductive portions within the cavity are electrically connected in parallel, and the chips mounted on different ones of the conductive portions within the cavity are electrically connected in a serial relationship.

4. The chip-mounting substrate of claim 2, wherein the chips are not mounted on one of the conductive portions disposed at one end, among the at least three or more of the conductive portions existing within the cavity, and the one of the conductive portions not mounted with the chips is electrically connected to electrode portions of the chips mounted on an adjoining one of the conductive portions.

5. The chip-mounting substrate of claim 1, wherein each of the insulation portions is bonded to each of the conductive portions through an anodizing layer formed on at least one surface of each of the conductive portions, so as to electrically isolate the conductive portions.

6. The chip-mounting substrate of claim 1, further comprising:

bumps formed at a predetermined height within the cavity on surfaces of the conductive portions isolated by the insulation portions, the bumps bonded to electrode portions formed in the chips.

7. The chip-mounting substrate of claim 6, wherein the electrode portions are formed on one surface of each of the chips which face the surfaces of the conductive portions, and each of the bumps is bonded to the electrode portions formed on one surface of each of the chips.

8. The chip-mounting substrate of claim 6, further comprising:

solders formed on surfaces of the bumps in order to solder the electrode portions and the bumps.

9. The chip-mounting substrate of claim 6, further comprising:

recess portions formed at a predetermined depth within the cavity,

wherein the bumps are formed at a predetermined height on the surfaces of the conductive portions in which the recess portions are formed, the bumps bonded to electrode portions formed in the chips.

10. The chip-mounting substrate of claim 6, further comprising:

plating layers formed at a predetermined height within the cavity on the surfaces of the conductive portions isolated by the insulation portions, the plating layers configured to bond the bumps and the conductive portions.

11. An uncut chip-mounting plate, comprising:

a plurality of conductive portions configured to apply voltages to at least two or more chips which are mounted on each of unit chip-mounting substrates defined on the uncut chip-mounting plate;

a plurality of insulation portions formed between the conductive portions in each of the unit chip-mounting substrates and configured to electrically isolate the conductive portions;

a cavity formed in a region of each of the unit chip-mounting substrates which includes at least three or more of the conductive portions and at least two or more of the insulation portions and depressed inward to form a space in which the chips are mounted; and

through-holes located on cutting lines of the uncut chip-mounting plate so as to penetrate and divide the insulation portions, wherein the cutting lines are lines along which the uncut chip-mounting plate is diced into unit chip-mounting substrates.

12. A chip package, comprising:

at least two or more chips;

a plurality of conductive portions configured to apply voltages to the chips;

a plurality of insulation portions formed between the conductive portions and configured to electrically isolate the conductive portions; and

a cavity formed in a region which includes at least three or more of the conductive portions and at least two or more of the insulation portions and depressed inward to form a space in which the chips are mounted,

wherein the chips are mounted on the conductive portions and are applied with voltages of opposite polarities from the conductive portions; and

through-holes are located on cutting lines of a chip-mounting plate so as to penetrate and divide the insulation portions, wherein the cutting lines are lines along which the chip-mounting plate is diced into unit chip-mounting substrates.