Multichip modules and methods of fabrication

• US 9,666,559 B2
• Filed: 07/24/2015
• Issued: 05/30/2017
• Est. Priority Date: 09/05/2014
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Invensas Corporation
• Inventors: Katkar, Rajesh, Shen, Hong, Wang, Liang
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US14/809,036
• Publication Number:
  US 20160071818A1
• Time in Patent Office: 676 Days
• Field of Search: 438667
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/33517 including layer connectors providing primarily mechanical support
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48135 Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73104 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73209 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/92124 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92133 : the second connecting process involving a bump connector
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/34 : Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/10 : the devices having separate containers
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/1511 : Structure
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F; “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips'"'"' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

Claims

1. A manufacturing process comprising:

(1) obtaining a plurality of assemblies, wherein obtaining each assembly of said assemblies comprises performing a process comprising;

obtaining a plurality of first modules for the assembly, each first module being a single-chip or multi-chip module comprising circuitry;

placing first molding compound in physical contact with each first module, and curing the first molding compound, to form a first structure in which the first modules are held together by at least the first molding compound, wherein the circuitry of each of at least two of the first modules has one or more first contact pads and one or more second contact pads on a bottom side of the first structure;

forming one or more layers on the bottom side of the first structure, the one or more layers providing bottom-side circuitry connected to one or more of the second contact pads on the bottom side of the first structure;

forming one or more first through-holes through the first molding compound, each first through-hole passing between top and bottom sides of the first molding compound; and

forming one or more first conductive vias in the one or more first through-holes, each first conductive via reaching and physically contacting the bottom-side circuitry, each first conductive via being accessible from the top side of the first molding compound;

obtaining one or more second modules each of which comprises circuitry with one or more first contact pads, each second module being a single-chip or multi-chip module; and

attaching each second module below the bottom side of the first structure to form a second structure in which each second module and the first modules are interconnected through the first contact pads of the first and second modules;

forming second molding compound on a bottom side of the second structure;

forming one or more second through-holes through the second molding compound, each second through-hole passing between top and bottom sides of the second molding compound; and

forming one or more second conductive vias in the one or more second through-holes, each second conductive via reaching and physically contacting the bottom-side circuitry, each second conductive via being accessible from the bottom side of the second molding compound;

(2) forming a stack of said assemblies, wherein for each two adjacent assemblies in the stack, at least one second conductive via of one of the two adjacent assemblies is attached to at least one first conductive via of the other one of the two adjacent assemblies.

7. The process of claim 1 wherein in each said assembly, in said attaching each second module, at least one second module underlies at least two corresponding first modules and has at least two first contact pads attached to respective two first contact pads of respective different ones of the corresponding first modules.

8. The process of claim 1 wherein in each said assembly, in said attaching each second module, at least one second module has at least two first contact pads attached to respective two first contact pads of respective different first modules with each attachment being by solder or diffusion bonding.

9. The process of claim 1 wherein in each said assembly, in said attaching each second module, at least one second module has at least two first contact pads attached to respective two first contact pads of respective different first modules with each attachment being by conductive or anisotropic adhesive.

10. The process of claim 9 wherein the adhesive is a polymeric adhesive.

11. The process of claim 10 wherein the adhesive is an organic polymeric adhesive.

12. The process of claim 1 wherein each said module is a chip.

2. A manufacturing process comprising:

obtaining a plurality of first modules each of which is a single-chip or multi-chip module comprising circuitry;

placing first molding compound in physical contact with each first module, and curing the first molding compound, to form a first structure in which the first modules are held together by at least the first molding compound, wherein the circuitry of each of at least two of the first modules has one or more first contact pads and one or more second contact pads on a bottom side of the first structure;

forming one or more layers on the bottom side of the first structure, the one or more layers providing bottom-side circuitry connected to one or more of the second contact pads on the bottom side of the first structure;

forming one or more first through-holes through the first molding compound, each first through-hole passing between top and bottom sides of the first molding compound; and

forming one or more first conductive vias in the one or more first through-holes, each first conductive via reaching and physically contacting the bottom-side circuitry, each first conductive via being accessible from the top side of the first molding compound.

3. The process of claim 2 further comprising:

obtaining one or more second modules each of which comprises circuitry with one or more first contact pads, each second module being a single-chip or multi-chip module; and

attaching each second module below the bottom side of the first structure to form an assembly in which each second module and the first modules are interconnected through the first contact pads of the first and second modules.

4. The process of claim 3 further comprising:

forming second molding compound on a bottom side of the assembly;

forming one or more second through-holes through the second molding compound, each second through-hole passing between top and bottom sides of the second molding compound; and

forming one or more second conductive vias in the one or more second through-holes, each second conductive via reaching and physically contacting the bottom-side circuitry, each second conductive via being accessible from the bottom side of the second molding compound.

5. A manufacturing process comprising:

obtaining a plurality of assemblies, wherein obtaining each of the assemblies comprises performing a process according to claim 4; and

forming a stack of said assemblies, wherein for each two adjacent assemblies in the stack, at least one second conductive via of one of the two adjacent assemblies is attached to at least one first conductive via of the other one of the two adjacent assemblies.

6. A manufacturing process comprising:

obtaining a plurality of assemblies, wherein obtaining each of the assemblies comprises performing a process according to claim 2; and

forming a stack of said assemblies, wherein for each two adjacent assemblies in the stack, at least one second conductive via of one of the two adjacent assemblies is attached to at least one first conductive via of the other one of the two adjacent assemblies.

13. The process of claim 3 wherein in said attaching each second module, at least one second module underlies at least two corresponding first modules and has at least two first contact pads attached to respective two first contact pads of respective different ones of the corresponding first modules.

14. The process of claim 3 wherein in said attaching each second module, at least one second module has at least two first contact pads attached to respective two first contact pads of respective different first modules with each attachment being by solder or diffusion bonding.

15. The process of claim 3 wherein in said attaching each second module, at least one second module has at least two first contact pads attached to respective two first contact pads of respective different first modules with each attachment being by conductive or anisotropic adhesive.

16. The process of claim 15 wherein the adhesive is a polymeric adhesive.

17. The process of claim 16 wherein the adhesive is an organic polymeric adhesive.

18. The process of claim 3 wherein each said module is a chip.

19. The process of claim 3 wherein each said module is a chip.