Compact three-dimensional memory

• US 9,666,641 B2
• Filed: 03/03/2015
• Issued: 05/30/2017
• Est. Priority Date: 04/14/2014
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Original Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Zarroli, Michael
• Application Number:
  US14/636,346
• Publication Number:
  US 20150295011A1
• Time in Patent Office: 819 Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors

Abstract

The present invention discloses a compact three-dimensional memory (3D-M_C). By forming simple switching devices (e.g., pass transistors) on the address-select lines, contact vias can be shared by the address-select lines in the same memory level, or from different memory levels. This leads to sparser and fewer contact vias.

Claims

1. A compact three-dimensional memory (3D-M_C) comprising at least a first memory level stacked above a semiconductor substrate with transistors thereon, said first memory level comprising:

a continuous and conductive first x-line;

a contact via coupling said first x-line with said semiconductor substrate;

a continuous and conductive y-line intersecting said first x-line at a first intersection, at least the portion of said first x-line at said first intersection comprising a heavily doped semiconductor material, wherein a first memory device is formed at said first intersection;

a continuous and conductive first control line intersecting said first x-line at a second intersection, the portion of said first x-line at said second intersection comprising a lightly doped semiconductor material, wherein a first switching device is formed at said second intersection, said first switching device is located between said first memory device and said contact via;

wherein said first switching device is configured to block current conduction in said first x-line in a first mode and allow current conduction in said first x-line in a second mode.

2. The memory according to claim 1, wherein said first memory device is a two-terminal device.

3. The memory according to claim 1, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM).

4. The memory according to claim 1, wherein said 3D-M comprises a three-dimensional random-access memory (3D-RAM).

5. The memory according to claim 1, wherein said first switching device is a three-terminal device.

6. The memory according to claim 5, wherein said first switching device is a transistor.

7. The memory according to claim 6, wherein said first switching device is a MOSFET, or a JFET.

8. A compact three-dimensional memory (3D-M_C) comprising at least a first memory level stacked above a semiconductor substrate with transistors thereon, said first memory level comprising:

a continuous and conductive first x-line;

a contact via coupling said first x-line with said semiconductor substrate;

a continuous and conductive y-line intersecting said first x-line at a first intersection, at least the portion of said first x-line at said first intersection comprising an upper highly conductive layer and a lower lightly doped semiconductor layer, wherein a first memory device is formed at said first intersection;

a continuous and conductive first control line intersecting said first x-line at a second intersection, the portion of said first x-line at said second intersection comprising said lightly doped semiconductor layer but not said highly conductive layer, wherein a first switching device is formed at said second intersection, said first switching device is located between said first memory device and said contact via;

wherein said first switching device is configured to block current conduction in said first x-line in a first mode and allow current conduction in said first x-line in a second mode.

9. The memory according to claim 8, wherein said first memory device is a two-terminal device.

10. The memory according to claim 8, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM).

11. The memory according to claim 8, wherein said 3D-M comprises a three-dimensional random-access memory (3D-RAM).

12. The memory according to claim 8, wherein said first switching device is a three-terminal device.

13. The memory according to claim 12, wherein said first switching device is a transistor.

14. The memory according to claim 12, wherein said first switching device is a MOSFET, or a JFET.

15. A compact three-dimensional memory (3D-M_C) comprising at least a first memory level stacked above a semiconductor substrate with transistors thereon, said first memory level comprising:

a continuous and conductive first x-line;

a contact via coupling said first x-line with said semiconductor substrate;

a continuous and conductive y-line intersecting said first x-line at a first intersection, at least the portion of said first x-line at said first intersection comprising a metallic material, wherein a first memory device is formed at said first intersection;

a continuous and conductive first control line intersecting said first x-line at a second intersection, the portion of said first x-line at said second intersection comprising a lightly doped semiconductor material, wherein a first switching device is formed at said second intersection, said first switching device is located between said first memory device and said contact via;

wherein said first switching device is configured to block current conduction in said first x-line in a first mode and allow current conduction in said first x-line in a second mode.

16. The memory according to claim 15, wherein said first memory device is a two-terminal device.

17. The memory according to claim 15, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM).

18. The memory according to claim 15, wherein said 3D-M comprises a three-dimensional random-access memory (3D-RAM).

19. The memory according to claim 15, wherein said first switching device is a three-terminal device.

20. The memory according to claim 19, wherein said first switching device is a transistor.