External storage device and method of manufacturing external storage device

• US 9,666,659 B2
• Filed: 03/10/2014
• Issued: 05/30/2017
• Est. Priority Date: 12/15/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nakashiba, Yasutaka, Ogawa, Kenta
• Primary Examiner(s): Wilson, Adrian S
• Assistant Examiner(s): RATHOD, ABHISHEK M
• Application Number:
  US14/203,037
• Publication Number:
  US 20140191363A1
• Time in Patent Office: 1,177 Days
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15183 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/117 : Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 2201/0949 : Pad close to a hole, not surrounding the hole
• CPC Class Codes: H05K 2201/09845 : Stepped hole, via, edge, bump or conductor
• CPC Class Codes: H05K 2203/0228 : Cutting, sawing, milling or shearing
• CPC Class Codes: H05K 2203/1316 : Moulded encapsulation of mounted components
• CPC Class Codes: H05K 2203/1572 : Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: Y10T 29/4902 : Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer.

Claims

1. An external storage device comprising:

an interconnect substrate comprising a first main surface, a first side, and an external terminal over the first main surface;

a first semiconductor chip comprising a storage device, an inductor connected to the storage device, and a driver circuit configured to control the inductor, the first semiconductor chip being disposed over the first main surface of the interconnect substrate; and

a sealing resin layer which seals the first semiconductor chip,

wherein the first main surface of the interconnect substrate comprises a first region and a second region more remote from the first side than the first region,

wherein the external terminal is over the first region of the first main surface, and the first semiconductor chip is over the second region of the first main surface,

wherein the external terminal comprises a first surface facing in a same direction as the first main surface of the interconnect substrate,

wherein the first surface of the external terminal comprises a first portion and a second portion more remote from the first side than the first portion,

wherein the sealing resin layer covers the second portion of the first surface of the external terminal without covering the first portion of the first surface of the external terminal.

2. The external storage device according to claim 1, wherein the first semiconductor chip comprises a first surface and a second surface opposite to the first surface of said semiconductor chip, and

wherein said second surface of said first semiconductor chip faces said first main surface of said interconnect substrate.

3. The external storage device according to claim 1, wherein said inductor outputs information stored in said storage device via an electromagnetic wave.

4. The external storage device according to claim 3, wherein said electromagnetic wave induces a current in a corresponding inductor of an external read device.

5. The external storage device according to claim 4, wherein said external read device reads said information based on an intensity of said induced current.

6. The external storage device according to claim 4, wherein a distance between said inductor and said corresponding inductor is less than 1 mm.

7. The external storage device according to claim 1, wherein a diameter of said inductor is less than 1 mm.

8. The external storage device according to claim 1, wherein a surface of said sealing resin layer runs parallel to a corresponding surface of said external terminal.

9. The external storage device according to claim 1, wherein said sealing resin layer includes a recessed portion for aiding communication of information stored in said storage device.

10. The external storage device according to claim 9, wherein said recessed portion includes a region overlapping said inductor.

11. The external storage device according to claim 1, further comprising a penetrating hole for alignment,

wherein said penetrating hole is formed in said interconnect substrate.

12. The external storage device according to claim 1, wherein the external terminal comprises a contact-type external terminal.

13. The external storage device according to claim 1, wherein the external terminal comprises a power supply terminal for connecting the driver circuit to a power supply.

14. An external storage device comprising:

an interconnect substrate comprising a first main surface, a first side, and an external terminal over the first main surface;

a first semiconductor chip comprising a storage element, the first semiconductor chip being disposed over the first main surface of the interconnect substrate;

a second semiconductor chip comprising an inductor connected to the storage element, and a driver circuit configured to control the inductor, the second semiconductor chip being disposed over the first main surface of the interconnect substrate; and

a sealing resin layer which seals said first and second semiconductor chips,

wherein the first main surface of the interconnect substrate comprises a first region and a second region more remote from the first side than the first region,

wherein the external terminal is over the first region of the first main surface, and the first semiconductor chip and the second semiconductor chip are over the second region of the first main surface,

wherein the external terminal comprises a first surface facing in a same direction as the first main surface of the interconnect substrate,

wherein the first surface of the external terminal comprises a first portion and a second portion more remote from the first side than the first portion,

wherein the sealing resin layer covers the second portion of the first surface of the external terminal without covering the first portion of the first surface of the external terminal.

15. The external storage device according to claim 14, wherein the first semiconductor chip comprises a first surface and a second surface opposite to the first surface of said first semiconductor chip, said second surface of said first semiconductor chip facing said first main surface of said interconnect substrate.

16. The external storage device according to claim 14, wherein said inductor comprises a plurality of inductors which are formed at said second semiconductor chip.

17. The external storage device according to claim 14, wherein an upper surface of said second semiconductor chip is higher than an upper surface of said first semiconductor chip when seen in a plan view.

18. The external storage device according to claim 14, wherein said external terminal is located at an end of said interconnect substrate which is opposite to an end of said interconnect substrate where said second semiconductor chip is located.

19. The external storage device according to claim 14, wherein said second semiconductor chip and said external terminal are located on opposite sides of a midpoint of said interconnect substrate.