Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device

• US 9,666,663 B2
• Filed: 08/09/2013
• Issued: 05/30/2017
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Laven, Johannes Georg, Schulze, Hans-Joachim, Cotorogea, Maria, Itani, Haybat, Haghofer, Andreas, Griebl, Erich
• Primary Examiner(s): Ward, Eric
• Assistant Examiner(s): ASHBAHIAN, ERIC K
• Application Number:
  US13/963,312
• Publication Number:
  US 20150041962A1
• Time in Patent Office: 1,390 Days
• Field of Search: 257623, 257E21382, 257E21383, 257328
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Claims

1. A semiconductor device comprising:

first cell trench structures comprising a first buried electrode;

second cell trench structures comprising a second buried electrode electrically separated from the first buried electrode, the first and second cell trench structures extending from a first surface into a semiconductor substrate,

first semiconductor mesas separating first and second cell trench structures and comprising a source zone of a first conductivity type and a body zone of a second conductivity type that is complementary to the first conductivity type at a first distance to the first surface, the source zone extending along the first surface from the first cell trench structure to the second cell trench structure, and the body zone comprising a contact zone along a sidewall portion of the first semiconductor mesa,

second semiconductor mesas separating first cell trench structures from each other, wherein the first cell trench structures comprise first insulator layers and first vertical sections of the first insulator layers separate the first buried electrodes from the first semiconductor mesas;

a capping layer on the first surface, the capping layer sandwiched between an electrode structure and the second semiconductor mesas and structurally separating the electrode structure from the second semiconductor mesas; and

first contact structures physically disconnected from the second semiconductor mesas, each first contact structure comprising a first section directly connected to the electrode structure in an opening of the capping layer and a second section sandwiched between one of the first semiconductor mesas and one of the first buried electrodes and directly adjoining the source and the contact zones in the respective first semiconductor mesa, wherein the first cell trench structure separates the second section from a neighboring one of the second semiconductor mesas, a vertical extension of the second section is greater than the first distance, and only one first contact structure is formed per first semiconductor mesa.

2. The semiconductor device of claim 1, wherein

first sidewalls of the second sections of the first contact structures directly adjoin the first semiconductor mesas, and

second sidewalls directly adjoin the first buried electrodes and at least the second sidewalls are tilted to the first surface by less than 90 degrees.

3. The semiconductor device of claim 2, wherein the first and second sidewalls taper with increasing distance to the first surface and the second sidewalls deviate to a higher degree from a normal to the first surface than the first sidewalls of the second sections of the first contact structures.

4. The semiconductor device of claim 1, further comprising second contact structures, each second contact structure formed in an opening of the capping layer and directly adjoining one of the first buried electrodes between two of the second semiconductor mesas.

5. The semiconductor device of claim 1, wherein the first insulator layer has a uniform width.

6. The semiconductor device of claim 1, wherein a width of the first insulator layer is equal to or less than a width of the second sections of the first contact structures.

7. The semiconductor device of claim 1, wherein the second sections of the first contact structures are located in a vertical projection of first vertical sections of the first insulator layers.