Manufacturable thin film gallium and nitrogen containing devices

• US 9,666,677 B1
• Filed: 12/23/2014
• Issued: 05/30/2017
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: Kyocera SLD Laser Incorporated (Kyocera Corporation)
• Original Assignee: Soraa Laser Diode, Inc. (Kyocera Corporation)
• Inventors: Raring, James W., McLaurin, Melvin, Sztein, Alexander, Hsu, Po Shan
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Mustapha, Abdulfattah
• Application Number:
  US14/580,693
• Time in Patent Office: 889 Days
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/452 : on AIII-BV compounds
• CPC Class Codes: H01L 29/475 : on AIII-BV compounds
• CPC Class Codes: H01L 29/66136 : PN junction diodes
• CPC Class Codes: H01L 29/66143 : Schottky diodes
• CPC Class Codes: H01L 29/66318 : Heterojunction transistors
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66916 : with a PN heterojunction gate
• CPC Class Codes: H01L 29/7786 : with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/868 : PIN diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 2933/0016 : relating to electrodes
• CPC Class Codes: H01L 33/0025 : comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/0066 : with a substrate not being a III-V compound
• CPC Class Codes: H01L 33/0075 : comprising nitride compounds
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 : within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/40 : Materials therefor
• CPC Class Codes: H01S 2301/173 : The laser chip comprising special buffer layers, e.g. dislocation prevention or reduction
• CPC Class Codes: H01S 5/0201 : Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
• CPC Class Codes: H01S 5/0213 : Sapphire, quartz or diamond based substrates
• CPC Class Codes: H01S 5/0215 : Bonding to the substrate
• CPC Class Codes: H01S 5/0216 : using an intermediate compound, e.g. a glue or solder
• CPC Class Codes: H01S 5/0217 : Removal of the substrate
• CPC Class Codes: H01S 5/04256 : characterised by the configuration
• CPC Class Codes: H01S 5/22 : having a ridge or stripe structure
• CPC Class Codes: H01S 5/320225 : polar orientation
• CPC Class Codes: H01S 5/32341 : blue laser based on GaN or GaP
• CPC Class Codes: H01S 5/34333 : with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
• CPC Class Codes: H01S 5/4025 : Array arrangements, e.g. constituted by discrete laser diodes or laser bar H01S5/42 takes precedence

Abstract

A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

providing a gallium and nitrogen containing substrate having a surface region;

forming a gallium and nitrogen containing epitaxial material overlying the surface region, the epitaxial material comprising a release material overlying the gallium and nitrogen containing substrate and at least an intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material or at least an n-type gallium and nitrogen containing region overlying the release material or at least a p-type gallium and nitrogen containing region overlying the release material or at least a combination of one or more of the n-type gallium and nitrogen containing region, the p-type gallium and nitrogen containing region, and the intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material;

patterning the epitaxial material and forming mesas to form a plurality of dice arranged in an array, each die corresponding to at least one semiconductor device and being arranged by a first pitch between the adjacent die in the array;

forming an interface region overlying the epitaxial material, the interface region comprising a metal, a semiconductor, dielectric, oxide, glass, or a polymer;

subjecting the release material to a photo electrochemical (PEC) etch to fully or partially remove the release material;

bonding the interface region to a carrier wafer to form a bonded structure, while maintaining the release material completely or partially etched away from the bonded structure, wherein the PEC etch of the release material is performed prior to the bonding step;

releasing the plurality of dice provided on the gallium and nitrogen containing substrate member to transfer a plurality of dice to the one or more carrier wafers wherein each pair of the transferred dice is configured with a second pitch between each pair of dice on a carrier wafer, the second pitch being equal or greater than the first pitch;

processing at least one of the plurality of dice on at least one of the carrier wafers to form at least a semiconductor device.

2. The method of claim 1, wherein the second pitch is larger than the first pitch.

3. The method of claim 1 whereupon the carrier wafer has a larger diameter and/or a larger total surface area than the gallium and nitrogen containing substrate.

4. The method of claim 1 further comprising transferring one or more additional dice from another substrate to populate the one or more carrier wafers, each of the one or more carrier wafers has a larger diameter than a diameter of the substrate.

5. The method of claim 1, wherein the carrier wafer is selected from a sapphire wafer, silicon carbide wafer, aluminum nitride wafer, silicon wafer, gallium arsenide wafer, diamond wafer, gallium nitride wafer, or an indium phosphide wafer.

6. The method of claim 1, wherein the release material is selected from GaN, InGaN, AlInGaN, or AlGaN.

7. The method of claim 1, wherein the PEC etch comprises KOH or any of its species.

8. The method of claim 1, wherein the PEC etch selectively removes the release region while leaving an anchor region intact to support the die before the selective bonding of the one or more die to the carrier wafer and the anchor region separates after the selective bonding of the one or more die;

wherein the anchor region is comprised of metal, semiconductor, dielectric, oxide, polymer, or a combination thereof.

9. The method of claim 1, wherein the PEC etch selectively removes the release region while leaving a metal anchor region in tact to support the die before the bonding of the one or more die to the one or more carrier wafer, and the metal anchor region separates after the bonding of the one or more die to the one or more carrier wafer;

wherein the metal anchor region is configured to provide an electrical short between an anode region and a cathode region to further facilitate the PEC etching process.

10. The method of claim 1, wherein the bonding comprising thermal bonding, thermocompressive bonding, plasma activated bonding, anodic bonding, chemical bonding, or combinations thereof;

wherein surface region of the gallium and nitrogen containing substrate is configured in a polar, semipolar, or non-polar orientation;

wherein the bond interface region comprising at least one of a metal-metal pair, dielectric-dielectric, oxide-oxide, semiconductor-semiconductor pair, a glass such as a spin-on-glass, soldering alloys, polymers, photoresists, wax, or a combination thereof.

11. The method of claim 1, wherein the substrate is reclaimed and prepared for reuse after transferring each of the plurality of dice to one or more carrier wafers.

12. The method of claim 1, wherein each of the die comprises one or more components, the one or more components being selected from at least one of an electrical contact bond pad, a light emitting region, a current spreading region, an optical cladding region, a drift region, an insulation region, an edge termination region, an emitter region, a base region, a collector region, a gate region, an isolation region, or a passivation region either alone or in any combination.

13. The method of claim 1, wherein the epitaxial material overlying the release material comprises an active region configured between an n-type gallium and nitrogen containing material such as GaN and a p-type gallium and nitrogen containing material such as GaN;

wherein the active region comprises one or more light emitting layers figured to emit electromagnetic radiation in the ultra-violet, violet, blue, green, or red wavelength regime;

wherein an n-type electrical contact is made to an n-type gallium and nitrogen containing material and a p-type electrical contact is made to a p-type gallium and nitrogen containing material;

wherein the device is operable as a light emitting diode (LED) under forward bias.

14. The method of claim 13, wherein the one or more light emitting layers are quantum well layers ranging in the thickness from 1 nm to 20 nm;

and wherein the p-type electrical contact comprising a silver metal, or a palladium metal, or a nickel metal, or a platinum metal, or a gold metal, or any combination thereof and wherein the n-type electrical contact comprising an aluminum metal, or a palladium metal, or a nickel metal, or a platinum metal, or a gold metal, or a titanium metal, or any combination thereof.

15. The method of claim 13, wherein the n-type and/or the p-type electrical contact comprising a transparent conductive oxide such as indium tin oxide.

16. The method of claim 1, wherein the epitaxial material overlying the release material comprises an active region configured between an n-type gallium and nitrogen containing material and a p-type gallium and nitrogen containing material;

wherein the active region comprises one or more light emitting layers figured to emit electromagnetic radiation in the violet, blue, green, or red wavelength regime;

forming a cladding region above and below the active region to confine an optical mode in the vertical direction;

forming a ridge waveguide structure to lateral confine the optical mode in the lateral direction;

forming a first facet region on the first end of the ridge waveguide region and a second facet region on the second end of the ridge waveguide region;

wherein an n-type electrical contact is made to the n-type gallium and nitrogen containing material and a p-type electrical contact is made to the p-type gallium and nitrogen containing material;

wherein the device is operable as a laser diode device under forward bias.

17. The method of claim 16, wherein the p-type electrical contact comprising a silver metal, or a palladium metal, or a nickel metal, or a platinum metal, or a gold metal, or any combination thereof and wherein the n-type electrical contact comprising an aluminum metal, a palladium metal, or a nickel metal, a platinum metal, or a gold metal, or a titanium metal, or any combination thereof.

18. The method of claim 1, wherein the epitaxial material overlying the release material comprises an n-type gallium and nitrogen containing material and an intrinsic or unintentionally doped drift region gallium nitrogen containing material;

wherein the intrinsic or drift region gallium and nitrogen containing material has a carrier concentration of less than about 1E17 cm<sup>−

3</sup> or less than about 5E16 cm<sup>−

3</sup> or less than about 1E16 cm<sup>−

3</sup> and a thickness of less than about 60 um, less than about 30 um, or less than about 10 um;

wherein the dopants in the intrinsic or unintentionally doped drift region gallium and nitrogen containing material are comprised of intentional dopants or non-intentional dopants or a combination thereof;

wherein an n-type electrical contact is made to the n-type gallium and nitrogen containing material and a Schottky electrical contact is made to the intrinsic gallium and nitrogen containing material;

wherein the device is operable as a Schottky barrier diode device.

19. The method of claim 18, wherein the n-type gallium and nitrogen containing material is comprised of gallium nitride and the intrinsic or unintentionally doped drift region gallium nitrogen containing material is comprised of gallium nitride.

20. The method of claim 18, wherein the Schottky electrical contact metal comprising at least a molybdenum metal, or at least a platinum metal, or at least a palladium metal, or at least a nickel metal, or at least a gold metal, or at least a chromium metal, or at least a tungsten metal, or any combination thereof;

and wherein the n-type electrical contact comprising at least an aluminum metal, or at least a gold metal, or at least a titanium metal, or any combination thereof.

21. The method of claim 18, wherein the intrinsic or unintentionally doped gallium and nitrogen containing material has a carrier concentration of less than 5E15 cm⁻

3 or less than 1E15 cm<sup>−

3</sup>.

22. The method of claim 18, wherein an edge termination region is formed to reduce the peak electric field along the Schottky contact edge;

wherein the edge termination is formed using a mesa structure, guard rings, field plates, high resistivity region by ion implantation, or a combination thereof;

wherein the Schottky diode device is a vertical structure.

23. The method of claim 1, wherein the epitaxial material overlying the release material comprises an n-type gallium and nitrogen containing material, an intrinsic or unintentionally doped drift region gallium nitrogen containing material, and a p-type gallium and nitrogen containing material;

wherein the intrinsic gallium and nitrogen containing material has a carrier concentration of less than about 1E17 cm<sup>−

3</sup> or less than about 5E16 cm<sup>−

3</sup> or less than about 1E16 cm<sup>−

3</sup> and a thickness of less than about 60 um, less than about 30 um, or less than about 10 um;

wherein the dopants in the intrinsic or unintentionally drift region are comprised of intentional dopants or non-intentional dopants or a combination thereof;

wherein an n-type electrical contact is made to an n-type gallium and nitrogen containing material and a p-type electrical contact is made to a p-type gallium and nitrogen containing material;

wherein the device is operable as a p-n diode device.

24. The method of claim 23, wherein the n-type gallium and nitrogen containing material is comprised of gallium nitride and the intrinsic or unintentionally doped drift region gallium and nitrogen containing material is comprised of gallium nitride.

25. The method of claim 23, wherein the p-type electrical contact comprising at least a palladium metal, or at least nickel metal, or at least nickel-gold metal, or at least platinum metal, or at least a gold metal, or any combination thereof;

and wherein the p-n diode device is a vertical p-n diode structure, wherein the n-type electrical contact comprising at least an aluminum metal, or at least a gold metal, or at least a titanium metal, or any combination thereof.

26. The method of claim 23, wherein the intrinsic or unintentionally doped drift region gallium and nitrogen containing material has a total active carrier concentration of less than 5E15 cm⁻

3 or less than 1E15 cm<sup>−

3</sup>.

27. The method of claim 1, further comprising wherein the epitaxial material overlying the release material comprises a first nitrogen containing material with a first bandgap and a second gallium and nitrogen containing material with a second bandgap;

wherein the first bandgap is greater than the second bandgap and wherein the first and second materials form a heterojunction interface;

forming a source region, a drain region, and a gate region;

wherein the semiconductor device is operable as a heterostructure field effect transistor or a high.

28. The method of claim 27, wherein the first nitrogen containing material is comprised of AlGaN or AlN and the second gallium and nitrogen containing material is comprised of GaN;

wherein the heterojunction interface forms a two dimensional electron gas.

29. The method of claim 27, wherein the source and drain metal contacts are comprised of a substantially ohmic contact and formed with a Ti/Al/Ni/Au metal stack, a Al/Ni/Au, an alternative Al containing metal stack, or a Ta-based metal stack.

30. The method of claim 27, wherein the gate contact is comprised of at least a metal such as Ni/Au, Pt, Pd, or Au.

31. The method of claim 27, wherein an insulator material is configured between the gate contact and the first nitrogen containing epitaxial material.

32. The method of claim 27, wherein the epitaxial material is comprised of a gallium and nitrogen containing cap layer overlying the first nitrogen containing material;

wherein the gallium and nitrogen containing cap layer is comprised from GaN, AlGaN, or InGaN.

33. The method of claim 1, wherein the epitaxial material overlying the release material comprises an n-type gallium and nitrogen containing material and a p-type gallium and nitrogen containing material;

wherein an n-type electrical contact is made to the n-type gallium and nitrogen containing material and a p-type electrical contact is made to the p-type gallium and nitrogen containing material; and

further comprising forming a source region, a drain region, and a gate region;

wherein the semiconductor device is operable as a junction field effect transistor.

34. The method of claim 1, wherein the epitaxial material overlying the release material comprises an n-type gallium and nitrogen containing material and a p-type gallium and nitrogen containing material;

wherein an n-type electrical contact is made to the n-type gallium and nitrogen containing material and a p-type electrical contact is made to the p-type gallium and nitrogen containing material;

wherein the semiconductor device is configured with a base region, and emitter region, and a collector region;

wherein the semiconductor device is operable as a bipolar junction transistor device or a heterostructure bipolar transistor.