Method for manufacturing semiconductor device

• US 9,666,698 B2
• Filed: 03/21/2016
• Issued: 05/30/2017
• Est. Priority Date: 03/24/2015
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US15/075,431
• Publication Number:
  US 20160284823A1
• Time in Patent Office: 435 Days
• CPC Class Codes: H01L 21/425 producing ion implantation
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then hydrogen is added to the oxide semiconductor using the first conductor as a mask.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming an oxide semiconductor over a substrate;

forming a first insulator over the oxide semiconductor;

forming a first conductor overlapping with the oxide semiconductor with the first insulator interposed therebetween;

after forming the first conductor, implanting an ion into the oxide semiconductor from the first conductor side; and

after implanting the ion, implanting hydrogen into the oxide semiconductor from the first conductor side,

wherein the ion is any of a helium ion, a neon ion, an argon ion, a krypton ion, and a xenon ion.

2. The method according to claim 1, wherein an oxygen vacancy is formed in the oxide semiconductor by implanting the ion.

3. The method according to claim 1, wherein implanting the ion comprises:

a first step of implanting the ion at an incident angle of greater than or equal to 10° and

less than or equal to 60°

with respect to a normal of a surface of the substrate; and

a second step of implanting the ion at an incident angle of greater than or equal to −

60° and

less than or equal to −

10°

with respect to the normal of the surface of the substrate.

4. The method according to claim 1, comprising:

forming a second insulator comprising an opening, over the substrate; and

forming a second conductor in the opening,

wherein the oxide semiconductor is formed over the second insulator and the second conductor, and

wherein the first conductor and the second conductor are overlapped with each other with the oxide semiconductor interposed therebetween.

5. The method according to claim 1, wherein the first conductor is a gate electrode.

6. The method according to claim 1, wherein part of the oxide semiconductor is exposed from the first insulator and the first conductor in implanting the ion into the oxide semiconductor.

7. A method for manufacturing a semiconductor device, comprising:

forming an oxide semiconductor over a substrate;

forming a first insulator over the oxide semiconductor;

forming a first conductor overlapping with the oxide semiconductor with the first insulator interposed therebetween;

after forming the first conductor, implanting an ion into the oxide semiconductor from the first conductor side;

after implanting the ion, implanting hydrogen into the oxide semiconductor from the first conductor side; and

after implanting hydrogen, performing a heat treatment on the oxide semiconductor.

8. The method according to claim 7, wherein an oxygen vacancy is formed in the oxide semiconductor by implanting the ion.

9. The method according to claim 7, wherein the ion is any of a helium ion, a neon ion, an argon ion, a krypton ion, and a xenon ion.

10. The method according to claim 7, wherein implanting the ion comprises:

a first step of implanting the ion at an incident angle of greater than or equal to 10° and

less than or equal to 60°

with respect to a normal of a surface of the substrate; and

a second step of implanting the ion at an incident angle of greater than or equal to −

60° and

less than or equal to −

10°

with respect to the normal of the surface of the substrate.

11. The method according to claim 7, comprising:

forming a second insulator comprising an opening, over the substrate; and

forming a second conductor in the opening,

wherein the oxide semiconductor is formed over the second insulator and the second conductor, and

wherein the first conductor and the second conductor are overlapped with each other with the oxide semiconductor interposed therebetween.

12. The method according to claim 7, wherein the first conductor is a gate electrode.

13. The method according to claim 7, wherein part of the oxide semiconductor is exposed from the first insulator and the first conductor in implanting the ion into the oxide semiconductor.

14. A method for manufacturing a semiconductor device, comprising:

forming an oxide semiconductor over a substrate;

forming a first insulator over the oxide semiconductor;

forming a first conductor overlapping with the oxide semiconductor with the first insulator interposed therebetween;

after forming the first conductor, implanting an ion into the oxide semiconductor from the first conductor side;

after implanting the ion, forming a second insulator on a side surface of the first conductor so that part of the oxide semiconductor is not overlapped with the second insulator; and

after forming the second insulator, implanting hydrogen into the oxide semiconductor from the first conductor side.

15. The method according to claim 14, wherein an oxygen vacancy is formed in the oxide semiconductor by implanting the ion.

16. The method according to claim 14, wherein the ion is any of a helium ion, a neon ion, an argon ion, a krypton ion, and a xenon ion.

17. The method according to claim 14, wherein implanting the ion comprises:

a first step of implanting the ion at an incident angle of greater than or equal to 10° and

less than or equal to 60°

with respect to a normal of a surface of the substrate; and

a second step of implanting the ion at an incident angle of greater than or equal to −

60° and

less than or equal to −

10°

with respect to the normal of the surface of the substrate.

18. The method according to claim 14, comprising:

forming a third insulator comprising an opening, over the substrate; and

forming a second conductor in the opening,

wherein the oxide semiconductor is formed over the third insulator and the second conductor, and

wherein the first conductor and the second conductor are overlapped with each other with the oxide semiconductor interposed therebetween.

19. The method according to claim 14, wherein the first conductor is a gate electrode.

20. The method according to claim 14, wherein part of the oxide semiconductor is exposed from the first insulator and the first conductor in implanting the ion into the oxide semiconductor.