Semiconductor device and method of manufacturing the same
First Claim
1. A semiconductor device comprising:
- a first insulating layer over a substrate, the first insulating layer including a first region adjacent to the substrate;
an oxide semiconductor layer over and in direct contact with the first insulating layer;
a gate electrode wherein the oxide semiconductor layer and the gate electrode overlap with each other; and
a gate insulating layer between the oxide semiconductor layer and the gate electrode,wherein a hydrogen concentration in the first region is less than or equal to 1.1×
1020 atoms/cm3,wherein the oxide semiconductor layer includes a channel formation region, a second region and a third region,wherein resistances of the second region and the third region are lower than a resistance of the channel formation region, andwherein the second region and the third region are formed in a self-aligned manner with respect to the gate insulating layer.
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Abstract
It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
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Citations
16 Claims
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1. A semiconductor device comprising:
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a first insulating layer over a substrate, the first insulating layer including a first region adjacent to the substrate; an oxide semiconductor layer over and in direct contact with the first insulating layer; a gate electrode wherein the oxide semiconductor layer and the gate electrode overlap with each other; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a hydrogen concentration in the first region is less than or equal to 1.1×
1020 atoms/cm3,wherein the oxide semiconductor layer includes a channel formation region, a second region and a third region, wherein resistances of the second region and the third region are lower than a resistance of the channel formation region, and wherein the second region and the third region are formed in a self-aligned manner with respect to the gate insulating layer. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device comprising:
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a first insulating layer over a substrate, the first insulating layer including a first region adjacent to the substrate; an oxide semiconductor layer over and in direct contact with the first insulating layer; a gate insulating layer over the oxide semiconductor layer; and a gate electrode over the gate insulating layer, wherein a hydrogen concentration in the first region is less than or equal to 1.1×
1020 atoms/cm3,wherein the oxide semiconductor layer includes a channel formation region, a second region and a third region, wherein resistances of the second region and the third region are lower than a resistance of the channel formation region, and wherein the second region and the third region are formed in a self-aligned manner with respect to the gate insulating layer. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A semiconductor device comprising:
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a first insulating layer over a substrate, the first insulating layer including a first region adjacent to the substrate; an oxide semiconductor layer over and in direct contact with the first insulating layer; a gate electrode over the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a hydrogen concentration in the first region is less than or equal to 1.1×
1020 atoms/cm3,wherein the oxide semiconductor layer includes a channel formation region, a second region and a third region, wherein resistances of the second region and the third region are lower than a resistance of the channel formation region, wherein an end portion of the second region and a first end portion of the gate insulating layer are aligned, and wherein an end portion of the third region and a second end portion of the gate insulating layer are aligned. - View Dependent Claims (13, 14, 15, 16)
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Specification