Semiconductor device
First Claim
1. A semiconductor device comprising a memory cell, the memory cell comprising a transistor and a capacitor,wherein the transistor comprises:
- an oxide semiconductor film comprising;
a channel formation region;
a pair of first regions with the channel formation region therebetween; and
a pair of second regions with the channel formation region therebetween;
a source electrode layer and a drain electrode layer over the oxide semiconductor film;
a gate electrode layer over the oxide semiconductor film; and
a gate insulating film between the oxide semiconductor film and the gate electrode layer,wherein the capacitor comprises one of the pair of the first regions and one of the pair of second regions,wherein the one of the pair of first regions of the capacitor functions as a dielectric of the capacitor,wherein the one of the pair of first regions and the one of the pair of second regions are stacked, and the other of the pair of first regions and the other of the pair of second regions are stacked,wherein a resistance value of the pair of first regions is higher than a resistance value of the pair of second regions, andwherein the oxide semiconductor film comprises a carrier concentration being less than or equal to 1×
1012 /cm3.
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Accused Products
Abstract
An object of the present invention is to provide a semiconductor device in which stored data can be held even when power is not supplied for a certain time. Another object is to increase the degree of integration of a semiconductor device and to increase the storage capacity per unit area. A semiconductor device is formed with a material capable of sufficiently reducing off-state current of a transistor, such as an oxide semiconductor material that is a wide-bandgap semiconductor. With the use of a semiconductor material capable of sufficiently reducing off-state current of a transistor, the semiconductor device can hold data for a long time. Furthermore, a wiring layer provided under a transistor, a high-resistance region in an oxide semiconductor film, and a source electrode are used to form a capacitor, thereby reducing the area occupied by the transistor and the capacitor.
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Citations
19 Claims
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1. A semiconductor device comprising a memory cell, the memory cell comprising a transistor and a capacitor,
wherein the transistor comprises: -
an oxide semiconductor film comprising; a channel formation region; a pair of first regions with the channel formation region therebetween; and a pair of second regions with the channel formation region therebetween; a source electrode layer and a drain electrode layer over the oxide semiconductor film; a gate electrode layer over the oxide semiconductor film; and a gate insulating film between the oxide semiconductor film and the gate electrode layer, wherein the capacitor comprises one of the pair of the first regions and one of the pair of second regions, wherein the one of the pair of first regions of the capacitor functions as a dielectric of the capacitor, wherein the one of the pair of first regions and the one of the pair of second regions are stacked, and the other of the pair of first regions and the other of the pair of second regions are stacked, wherein a resistance value of the pair of first regions is higher than a resistance value of the pair of second regions, and wherein the oxide semiconductor film comprises a carrier concentration being less than or equal to 1×
1012 /cm3. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device comprising a memory cell, the memory cell comprising a transistor and a capacitor,
wherein the transistor comprises: -
an oxide semiconductor film comprising; a channel formation region; a pair of first regions with the channel formation region therebetween; and a pair of second regions with the channel formation region therebetween; a source electrode layer and a drain electrode layer over the oxide semiconductor film; a gate electrode layer over the oxide semiconductor film; and a gate insulating film between the oxide semiconductor film and the gate electrode layer, wherein the capacitor comprises one of the pair of first regions and one of the pair of second regions, wherein the one of the pair of first regions of the capacitor functions as a dielectric of the capacitor, wherein the one of the pair of first regions and the one of the pair of second regions are stacked, and the other of the pair of first regions and the other of the pair of second regions are stacked, wherein a resistance value of the pair of first regions is higher than a resistance value of the pair of second regions, and wherein an off-state current per micrometer of a channel width of the transistor is 1×
10−
19 A/μ
m or less. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification