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Wire bond sensor package

  • US 9,666,730 B2
  • Filed: 07/27/2015
  • Issued: 05/30/2017
  • Est. Priority Date: 08/18/2014
  • Status: Active Grant
First Claim
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1. A packaged chip assembly, comprising:

  • a semiconductor chip that includes;

    a first substrate of semiconductor material having first top and first bottom surfaces,a semiconductor device integrally formed on or in the first top surface, andfirst bond pads at the first top surface electrically coupled to the semiconductor device;

    a second substrate that includes;

    second top and second bottom surfaces,a first aperture extending between the second top and second bottom surfaces,one or more second apertures extending between the second top and second bottom surfaces,second bond pads at the second top surface,third bond pads at the second bottom surface, andconductors electrically coupled to the second bond pads and the third bond pads;

    wherein the first top surface is secured to the second bottom surface such that the semiconductor device is aligned with the first aperture, and each of the first bond pads is aligned with one of the one or more second apertures; and

    a plurality of wires each electrically connected between one of the first bond pads and one of the second bond pads and each passing through one of the one or more second apertures.

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