Wire bond sensor package

• US 9,666,730 B2
• Filed: 07/27/2015
• Issued: 05/30/2017
• Est. Priority Date: 08/18/2014
• Status: Active Grant

• Current Assignee: Optiz, Inc.
• Original Assignee: Optiz, Inc.
• Inventors: Oganesian, Vage, Lu, Zhenhua
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US14/809,921
• Publication Number:
  US 20160049526A1
• Time in Patent Office: 673 Days
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10155 being other than a cuboid
• CPC Class Codes: H01L 2924/10156 at the periphery
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/18 : Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

A packaged chip assembly with a semiconductor substrate, a semiconductor device integrally formed on or in the substrate'"'"'s top surface, and first bond pads at the substrate'"'"'s top surface electrically coupled to the semiconductor device. A second substrate includes a first aperture and one or more second apertures extending therethrough, second and third bond pads at the second substrate'"'"'s top and bottom surfaces, respectively, and conductors electrically coupled to the second and third bond pads. The semiconductor substrate'"'"'s top surface is secured to the second substrate'"'"'s bottom surface such that the semiconductor device is aligned with the first aperture, and each of the first bond pads is aligned with one of the second apertures. A plurality of wires are each electrically connected between one of the first bond pads and one of the second bond pads and each passing through one of the one or more second apertures.

Claims

1. A packaged chip assembly, comprising:

a semiconductor chip that includes;

a first substrate of semiconductor material having first top and first bottom surfaces,

a semiconductor device integrally formed on or in the first top surface, and

first bond pads at the first top surface electrically coupled to the semiconductor device;

a second substrate that includes;

second top and second bottom surfaces,

a first aperture extending between the second top and second bottom surfaces,

one or more second apertures extending between the second top and second bottom surfaces,

second bond pads at the second top surface,

third bond pads at the second bottom surface, and

conductors electrically coupled to the second bond pads and the third bond pads;

wherein the first top surface is secured to the second bottom surface such that the semiconductor device is aligned with the first aperture, and each of the first bond pads is aligned with one of the one or more second apertures; and

a plurality of wires each electrically connected between one of the first bond pads and one of the second bond pads and each passing through one of the one or more second apertures.

2. The assembly of claim 1, further comprising:

a third substrate secured to the second top surface and covering the first aperture.

3. The assembly of claim 2, wherein the third substrate is optically transparent or semitransparent.

4. The assembly of claim 3, wherein the semiconductor device is one of an image sensor, an infrared sensor, and a light sensor.

5. The assembly of claim 1, further comprising:

encapsulant covering the wires and filling the one or more second apertures.

6. The assembly of claim 1, further comprising:

encapsulant extending from the second bottom surface, along a sidewall of the first substrate, and to the first bottom surface.

7. The assembly of claim 1, further comprising:

a third substrate that includes;

third top and third bottom surfaces, and

fourth bond pads at the third top surface;

electrical interconnects each electrically coupling one of the third bond pads to one of the fourth bond pads.

8. The assembly of claim 1, further comprising:

a plurality of holes extending between the second top surface and the second bottom surface, wherein the conductors are conductive material in the plurality of holes each extending between one of the second bond pads and one of the third bond pads.

9. A packaged chip assembly, comprising:

a semiconductor chip that includes;

a first substrate of semiconductor material having first top and first bottom surfaces,

a semiconductor device integrally formed on or in the first top surface,

first bond pads at the first top surface electrically coupled to the semiconductor device,

one or more trenches formed into the first top surface, and

a plurality of conductive traces each having a first portion electrically connected to one of the first bond pads, a second portion extending over and insulated from the first top surface, and a third portion extending down into one of the one or more trenches;

a second substrate that includes;

second top and second bottom surfaces,

second bond pads at the second top surface,

third bond pads at the second bottom surface, and

conductors electrically coupled to the second bond pads and to the third bond pads;

wherein the first bottom surface is secured to the second top surface;

a plurality of wires each electrically connected between one of the third portions of one of the plurality of conductive traces and one of the second bond pads; and

a third substrate that includes;

third top and third bottom surfaces, and

fourth bond pads at the third top surface;

electrical interconnects each electrically coupling one of the third bond pads to one of the fourth bond pads.

10. The assembly of claim 9, further comprising:

a fourth substrate secured to the first top surface and disposed over the semiconductor device.

11. The assembly of claim 10, further comprising:

adhesive material disposed between the fourth substrate and the first top surface.

12. The assembly of claim 10, wherein the fourth substrate comprises multiple sheets of single crystal sapphire layered in different crystal plane orientations.

13. The assembly of claim 10, wherein the fourth substrate is optically transparent or semitransparent.

14. The assembly of claim 13, wherein the semiconductor device is one of an image sensor, an infrared sensor, and a light sensor.

15. The assembly of claim 9, further comprising:

encapsulant covering the wires and the conductive traces.

16. A packaged chip assembly, comprising:

a semiconductor chip that includes;

a first substrate of semiconductor material having first top and first bottom surfaces,

a semiconductor device integrally formed on or in the first top surface,

first bond pads at the first top surface electrically coupled to the semiconductor device,

one or more trenches formed into the first top surface, and

a plurality of conductive traces each having a first portion electrically connected to one of the first bond pads, a second portion extending over and insulated from the first top surface, and a third portion extending down into one of the one or more trenches;

a second substrate that includes;

second top and second bottom surfaces,

second bond pads at the second top surface,

third bond pads at the second bottom surface, and

conductors electrically coupled to the second bond pads and to the third bond pads;

wherein the first bottom surface is secured to the second top surface;

a plurality of wires each electrically connected between one of the third portions of one of the plurality of conductive traces and one of the second bond pads; and

a third substrate secured to the first top surface and disposed over the semiconductor device, wherein the third substrate is secured directly to the first top surface without any intervening materials.