Wafer level packaging of multiple light emitting diodes (LEDs) on a single carrier die

• US 9,666,764 B2
• Filed: 03/13/2013
• Issued: 05/30/2017
• Est. Priority Date: 04/09/2012
• Status: Active Grant

• Current Assignee: Creeled Incorporated
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Haberern, Kevin, Bergmann, Michael John, Dillon, Alan Wellford
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Hatzilambrou, Mark
• Application Number:
  US13/801,743
• Publication Number:
  US 20130264592A1
• Time in Patent Office: 1,539 Days
• Field of Search: 257 91, 257 98
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/14131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/14155 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/14177 Combinations of arrays with different layouts
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/81895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 27/156 : two-dimensional arrays
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2933/0016 : relating to electrodes
• CPC Class Codes: H01L 2933/0033 : relating to semiconductor body packages
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/22 : Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/382 : the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/405 : Reflective materials
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/50 : Wavelength conversion elements
• CPC Class Codes: H01L 33/60 : Reflective elements
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/64 : Heat extraction or cooling elements

Abstract

An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide multiple LED dies that are joined to a single carrier die. The multiple LED dies on the single carrier die are connected in series and/or in parallel by interconnection in the LED dies and/or in the single carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. Related devices and fabrication methods are described.

Claims

1. A Light Emitting Diode (LED) chip, comprising:

an LED substrate including a plurality of LED dies, a respective LED die including an anode and a cathode;

a patterned internal interconnection layer that is internal to the plurality of LED dies and that is configured to selectively electrically connect the anodes and cathodes of the plurality of LED dies in series and/or in parallel internal to the plurality of LED dies;

an LED die anode contact that is electrically connected to at least one of the anodes; and

an LED die cathode contact that is electrically connected to at least one of the cathodes,

wherein the patterned internal interconnection layer that is internal to the plurality of LED dies includes a first patterned internal interconnection layer face and a second patterned internal interconnection layer face that is opposite the first patterned internal interconnection layer face,

wherein each of the plurality of LED dies includes a first layer that is on the first patterned internal interconnection layer face opposite the second patterned internal interconnection layer face, and a second layer that is on the second patterned internal interconnection layer face opposite the first patterned internal interconnection layer face,

wherein the LED die anode contact penetrates through the first and second layers, penetrates through the first patterned internal interconnection layer face, penetrates through the second patterned internal interconnection layer face, electrically connects to the patterned internal interconnection layer and electrically connects to the at least one of the anodes, and

wherein the LED die cathode contact penetrates through the first and second layers, penetrates through the first patterned internal interconnection layer face, penetrates through the second patterned internal interconnection layer face, electrically connects to the patterned internal interconnection layer and electrically connects to the at least one of the cathodes.

2. The LED chip according to claim 1 wherein the first and second layers comprise first and second insulating layers, respectively, and the patterned internal interconnection layer comprises a patterned internal metal layer.

3. The LED chip according to claim 1 further comprising:

a carrier die having first and second opposing faces, the carrier die having a first anode contact and a first cathode contact on the first face and a second anode contact and a second cathode contact on the second face, the carrier die being joined to the LED substrate so that the plurality of LED dies are adjacent the first face, the first anode contact is electrically connected to the LED die anode contact and the first cathode contact is electrically connected to the LED die cathode contact.

4. The LED chip according to claim 3 wherein the LED substrate includes beveled sidewalls between adjacent LED dies.

5. The LED chip according to claim 4 wherein the LED substrate includes a beveled edge at a periphery thereof.

6. The LED chip according to claim 4 further comprising a wavelength conversion material layer on the LED substrate remote from the carrier die, and extending onto the beveled sidewalls between adjacent LED dies, the wavelength conversion material layer including opposing surfaces that both conform to the beveled sidewalls between adjacent LED dies.

7. The LED chip according to claim 5 further comprising a wavelength conversion material layer on the LED substrate remote from the carrier die, and extending onto the beveled sidewalls between adjacent LED dies and onto the beveled edge at the periphery of the LED substrate, the wavelength conversion material layer including opposing surfaces that both conform to the beveled sidewalls between adjacent LED dies and to the beveled edge at the periphery of the LED substrate.

8. The LED chip according to claim 7 wherein the wavelength conversion material layer further extends onto a sidewall of the LED die at the periphery of the LED substrate.

9. The LED chip according to claim 3 further comprising:

a mounting substrate on the second face of the carrier die and electrically connected to the second anode contact and the second cathode contact.

10. The LED chip according to claim 3 in combination with:

a light fixture housing in which the carrier die is mounted to provide a light fixture.

11. The LED chip according to claim 3 wherein the carrier die further comprises at least one thermal contact on the first and/or second face.

12. The LED chip according to claim 3 wherein the carrier die comprises silicon.

13. The LED chip according to claim 3 wherein the carrier die comprises an internal reflector between the first and second faces thereof.

14. The LED chip according to claim 1 wherein the patterned internal interconnection layer comprises:

a crack reducing layer that is configured to reduce propagation of cracks between the first and second layers; and

a crack reducing layer extension that extends from the crack reducing layer to selectively electrically connect the anodes and cathodes of the plurality of LED dies in series and/or in parallel internal to the plurality of LED dies.

15. A Light Emitting Diode (LED) chip, comprising:

a plurality of LED dies in a common substrate, a respective one of which includes an anode contact and a cathode contact on a face thereof;

a carrier die having first and second opposing faces, a plurality of internal contacts on the first face and an external anode contact and an external cathode contact on the second face, wherein the plurality of LED dies in the common substrate includes a patterned internal interconnection layer that is internal to the plurality of LED dies and that is configured to electrically connect the anode and cathode contacts of the plurality of LED dies in series and/or in parallel internal to the plurality of LED dies;

the plurality of LED dies and the carrier die being joined to one another so that the anode and cathode contacts of the LED dies are adjacent the first face of the carrier die and the anode and cathode contacts of the plurality of LED dies are connected in series and/or in parallel,

wherein the patterned internal interconnection layer that is internal to the plurality of LED dies includes a first patterned internal interconnection layer face and a second patterned internal interconnection layer face that is opposite the first patterned internal interconnection layer face,

wherein each of the plurality of LED dies includes a first layer that is on the first patterned internal interconnection layer face opposite the second patterned internal interconnection layer face, and a second layer that is on the second patterned internal interconnection layer face opposite the first patterned internal interconnection layer face,

wherein the anode contact penetrates through the first and second layers, penetrates through the first patterned internal interconnection layer face, penetrates through the second patterned internal interconnection layer face and electrically connects to the patterned internal interconnection layer, and

wherein the cathode contact penetrates through the first and second layers, penetrates through the first patterned internal interconnection layer face, penetrates through the second patterned internal interconnection layer face and electrically connects to the patterned internal interconnection layer.

16. The LED chip according to claim 15 wherein the patterned internal interconnection layer comprises:

a crack reducing layer that is configured to reduce propagation of cracks between the first and second layers; and

a crack reducing layer extension that extends from the crack reducing layer to selectively electrically connect the anodes and cathodes of the plurality of LED dies in series and/or in parallel internal to the plurality of LED dies.