Systems and methods for starting up analog circuits

• US 9,667,240 B2
• Filed: 03/28/2012
• Issued: 05/30/2017
• Est. Priority Date: 12/02/2011
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Moscaluk, Gary
• Primary Examiner(s): Chen, Sibin
• Application Number:
  US13/432,038
• Publication Number:
  US 20130265089A1
• Time in Patent Office: 1,889 Days
• Field of Search: 327 51, 327 77, 327 78, 327530, 327538, 327540, 327541, 327543, 327142, 327143, 327198, 323238, 323321, 323901
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

Circuits, systems, and methods for starting up analog devices are provided. One circuit includes an output node at an output voltage (VOUT), a comparator configured to be coupled to a reference voltage (VREF), a feedback loop coupling the output node to the comparator, and a turbo circuit coupled between the output and the output node. The turbo circuit is configured to increase VOUT, the comparator is configured to compare VOUT and VREF, and the turbo circuit is enabled and disabled based on the comparison of VOUT and VREF. One system includes an analog device coupled to the above circuit. A method includes enabling the startup portion to start up the driver portion when VOUT is outside a predetermined voltage of VREF, disabling the startup portion when VOUT is within the predetermined voltage, and enabling the driver portion to drive the analog device subsequent to disabling the startup portion.

Claims

1. A startup circuit, comprising:

an output node at an output voltage (VOUT);

an operational amplifier coupled to the output node;

a comparator comprising a first input configured to be coupled to a reference voltage (VREF), a second input, and an output;

a feedback loop coupling the output node to the second input; and

a turbo circuit coupled between the output and the output node and configured to be coupled to a supply voltage (VPWR), the turbo circuit is configured to increase VOUT, wherein;

the comparator is configured to compare VOUT and VREF, the turbo circuit is disabled when the VOUT at the output node is within a predetermined voltage of the VREF, the operational amplifier starts up when the VOUT at the output node is outside the predetermined voltage of the VREF, and the operational amplifier drives a load that is coupled to the output node.

2. The startup circuit of claim 1, wherein the turbo circuit comprises:

a first p-channel metal oxide semiconductor field-effect transistor (pMOSFET);

a second pMOSFET coupled to the first pMOSFET; and

a first n-channel metal oxide semiconductor field-effect transistor (nMOSFET).

3. The startup circuit of claim 2, further comprising control logic coupled between the comparator and the turbo circuit, the control logic configured to enable and disable the turbo circuit based on a signal received from the comparator.

4. The startup circuit of claim 3, wherein the comparator is configured to trip when VOUT is within the predetermined voltage of VREF, the signal indicative of whether VOUT is within the predetermined voltage of VREF.

5. The startup circuit of claim 4, wherein the predetermined voltage is a hysteresis in the range of about 5 mV to about 50 mV of VREF.

6. The startup circuit of claim 4, wherein the predetermined voltage is within 5 mV of VREF.

7. The startup circuit of claim 3, wherein:

the first pMOSFET comprises a first gate, a first source, and a first drain;

the second pMOSFET comprises a second gate, a second source, and a second drain;

the first nMOSFET comprises a third gate, a third source, and a third drain;

the first gate is coupled to the control logic, the first source is coupled to VPWR, and the first drain is coupled to the second source;

the second gate is coupled to VGND and the second drain is coupled to the third drain;

and the third gate is coupled to VREF and the third source is coupled to VOUT.

8. The startup circuit of claim 1, wherein the operational amplifier comprises a third input coupled to VREF, a fourth input coupled to the feedback loop, and a second output coupled to a third output of the turbo circuit.

9. The startup circuit of claim 8, further comprising an n-follower device coupled between the output node and a node coupled to the second output and the third output.

10. The startup circuit of claim 9, wherein the n-follower device comprises an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), the nMOSFET comprising:

a gate coupled to the node;

a drain coupled to VPWR;

a source coupled to the output node; and

a bulk coupled to the output node.

11. The startup circuit of claim 1, wherein the startup circuit is coupled between a reference voltage generator and one or more analog devices.

12. A method of operating a startup circuit that includes a comparator and a turbo circuit, the method comprising:

enabling the comparator by applying a reference voltage (VREF) to a first input of the comparator, wherein the comparator comprises an output, the first input, and a second input, wherein the second input is coupled via a feedback loop to an output node at an output voltage (VOUT);

applying a supply voltage (VPWR) to the turbo circuit, wherein the turbo circuit is coupled between the output of the comparator and the output node;

the turbo circuit increasing the VOUT based on a signal from the output of the comparator;

starting up an operational amplifier when the VOUT at the output node is outside a predetermined voltage of the VREF;

the comparator comparing the VOUT to the VREF; and

disabling the turbo circuit when the VOUT is within the predetermined voltage of the VREF;

wherein the operational amplifier is enabled to drive a load coupled to the output node.

13. The method of claim 12, wherein the startup circuit further comprises control logic coupled between the comparator and the turbo circuit, and wherein the method further comprises:

the control logic enabling and disabling the turbo circuit in response to receiving the signal from the output of the comparator.

14. The method of claim 12, wherein the comparator comparing the VOUT to the VREF comprises the comparator tripping when the VOUT is within a predetermined voltage of the VREF, and wherein the signal from the output of the comparator is indicative of whether the VOUT is within the predetermined voltage of the VREF.

15. The method of claim 14, wherein the predetermined voltage is a hysteresis in the range of about 5 mV to about 50 mV of the VREF.

16. The method of claim 14, wherein the predetermined voltage is within 5 mV of the VREF.

17. The method of claim 12, wherein the method further comprises:

enabling the turbo circuit when the VOUT is outside of about 5 mV of the VREF; and

disabling the turbo circuit when the VOUT is within about 5 mV of the VREF.

18. The method of claim 12, further comprising:

enabling the operational amplifier to drive the load subsequent to disabling the turbo circuit.

19. The method of claim 18, wherein the operational amplifier comprises a third input coupled to the VREF, a fourth input coupled to the feedback loop, and a second output coupled to a third output of the turbo circuit.