Communication channel calibration for drift conditions

• US 9,667,406 B2
• Filed: 04/24/2015
• Issued: 05/30/2017
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: K.Mizra LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Hampel, Craig E., Perego, Richard E.
• Primary Examiner(s): Tran, Khai
• Application Number:
  US14/695,597
• Publication Number:
  US 20150229468A1
• Time in Patent Office: 767 Days
• Field of Search: 375355, 375219, 375222, 375257, 375295, 370516
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/12 Compensating for variations in line impedance
• CPC Class Codes: H04L 7/0016 correction of synchronization errors
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Claims

1. A memory controller integrated circuit (IC), comprising:

a receiver to sample read data arriving at the memory controller IC from a memory device, the receiver to sample the read data according to a sampling phase defined relative to a sample clock;

logic to establish an initial value of the sampling phase during a calibration operation; and

logic to compensate for drift between the sampling phase and timing associated with the read data transmitted by the memory device, to adjust the initial value in response to drift detected subsequent to establishment of the initial value.

2. The memory controller IC of claim 1, wherein the logic to establish the initial value includes logic to vary the sampling phase while the receiver is to sample test data transmitted by the memory controller IC, logic to read back the test data sampled by the memory device while the sampling phase has been varied, logic to responsively identify a data window, and logic to establish the initial value dependent on timing of the data window.

3. The memory controller IC of claim 1, wherein:

the logic to establish the initial value includes logic to transmit a symbol pattern to the memory device during the calibration operation;

the receiver is to, during the calibration operation, sample a sequence of values received back from the memory device;

the logic to establish the initial value includes logic is to compare the symbol pattern and the sequence to detect mismatch; and

the logic to vary the sampling phase to identify the data window is to identify the data window dependent on detected mismatch.

4. The memory controller IC of claim 3, wherein the logic to establish the initial value includes a pseudorandom bit pattern generator, and where the symbol pattern comprises a pseudorandom bit pattern of at least 2⁷−

1 bits.

5. The memory controller IC of claim 1, wherein the logic to compensate is to obtain test data from the memory device via a communication channel, is to test the test data, and is to incrementally adjust the value upward or downward in order to maintain a desired phase relationship between the sample clock and the read data transmitted by the memory device.

6. The memory controller IC of claim 5, wherein:

the memory controller IC further comprises storage to store information defining a current value to be used by the memory controller IC to define the sampling phase;

the logic to compensate is to, on a repeated, intermittent basis, (1) obtain the test data from the memory device using the information, (2) test the test data, (3) incrementally adjust the current value in response to drift detected relative to the current value, to define a new value, and (4) store the new value in the storage for ensuing use as the current value.

7. The memory controller IC of claim 6, wherein:

the logic to compensate is further to perform (1)-(4) on a periodic basis;

the memory controller further comprises a transmitter to transmit write data from the memory controller IC to the memory device, the write data being transmitted according to a transmit phase defined relative to a transmit clock;

the memory controller IC further comprises

logic to establish an initial value of the transmit phase during a calibration operation; and

logic to compensate for drift between the initial value of the transmit phase and timing associated with the write data received by the memory device, and to adjust the initial value of the transmit phase in response to drift detected subsequent to establishment of the initial value of the transmit phase;

wherein the logic to compensate for drift between the initial value of the transmit phase and the time associated with the write data is to transmit second test data from the memory device via the communication channel, is to read back and test the second test data, and is to incrementally adjust the initial value upward or downward in order to maintain a desired phase relationship between the transmit clock and second test data transmitted to the memory device.

8. The memory controller IC of claim 1, wherein the logic to establish the initial value for the sampling phase is to detect occurrence of at least one edge, at the receiver, associated with a transition between data values, and to establish the initial value for the sampling phase dependent on timing of the at least one edge.

9. The memory controller IC of claim 8, wherein the logic to establish the initial value is to detect occurrence of two different edges, at the receiver, associated with a data symbol period for test data received at the receiver, and to establish the operational value for the sampling phase dependent on timing of each of the two different edges.

10. The memory controller IC of claim 1, wherein the logic to compensate for drift includes logic to periodically identify variation in a timing point associated with the read data where the variation is induced by temperature change and to adjust the value of the sampling phase to track said variation.

11. A memory controller integrated circuit (IC), comprising:

a receiver to sample read data arriving at the memory controller IC from a memory device, the receiver to sample the data according to a sampling phase defined relative to a sample clock;

logic to establish an initial value of the sampling phase during a calibration operation; and

logic to compensate for drift between the sampling phase and timing associated with the read data transmitted by the memory device, and to adjust the value of the sampling phase in response to drift detected subsequent to establishment of the initial value;

wherein the logic to compensate is to obtain test data from the memory device via a communication channel, is to test the test data, and is to incrementally adjust the value of the sampling phase in order to maintain a predetermined phase relationship between the sample clock and the read data transmitted by the memory device.

12. The memory controller IC of claim 11, wherein:

the memory controller IC further comprises storage to store information defining a current value to be used by the memory controller IC to define the sampling phase;

the logic to compensate is to, on a repeated, intermittent basis, (1) obtain the test data from the memory device using the information, (2) test the test data, (3) incrementally adjust the current value in response to drift detected relative to the current value, to define a new value, and (4) store the new value in the storage for ensuing use as the current value.

13. The memory controller IC of claim 12, wherein:

the logic to compensate is further to perform (1)-(4) on a periodic basis;

the memory controller further comprises a transmitter to transmit write data from the memory controller IC to the memory device according to a transmit phase defined relative to a transmit clock;

the memory controller IC further comprises

logic to establish an initial value of the transmit phase during a calibration operation; and

logic to compensate for drift between the transmit phase and timing associated with the write data received by the memory device, to adjust the value of the transmit phase in response to drift detected subsequent to establishment of the initial value of the transmit phase;

wherein the logic to compensate for drift between the value of the transmit phase and the time associated with the write data is to transmit second test data from the memory device via the communication channel, is to read back and test the second test data, and is to incrementally adjust the value of the transmit phase upward or downward in order to maintain a desired phase relationship between the transmit clock and second test data transmitted to the memory device.

14. The memory controller IC of claim 11, wherein the logic to establish the initial value is to detect occurrence of two different edges, at the receiver, associated with a data symbol period for test data received at the receiver, and to establish the operational value for the sampling phase dependent on timing of the two different edges.

15. The memory controller IC of claim 11, wherein the logic to establish the initial value is to establish the operational value for the sampling phase at an approximate center point between timing of the two different edges.

16. A memory controller integrated circuit (IC), comprising:

a receiver to sample read data arriving at the memory controller IC from a memory device according to a sampling phase defined relative to a sample clock;

logic to establish an initial value of the sampling phase during a calibration operation; and

logic to periodically adjust the value of the sampling phase in order to compensate for drift between the sampling phase and timing associated with the read data transmitted by the memory device;

wherein the logic to compensate is to obtain test data from the memory device via a communication channel, is to test the test data, and is to incrementally adjust the value of the sampling phase upward or downward, in order to maintain a desired phase relationship between the sample clock and read data transmitted by the memory device, in a manner adapted to compensate for variation between the sample clock and timing of the read data which is induced by temperature change.

17. A method of operating a memory controller integrated circuit (IC), comprising:

sampling read data arriving at the memory controller IC from a memory device according to a sampling phase defined relative to a sample clock;

establishing an initial value of the sampling phase during a calibration operation; and

adjusting the value of the sampling phase in response to drift between the sampling phase and timing associated with the read data transmitted by the memory device, the drift detected subsequent to establishment of the initial value.

18. The method of claim 17, wherein the method further comprises obtaining test data from the memory device via a communication channel, testing the test data, and incrementally adjusting the value upward or downward in order to maintain a desired phase relationship between the sample clock and the read data transmitted by the memory device.

19. The method of claim 18, wherein the method further comprises:

defining a current value to be used by the memory controller IC to define the sampling phase; and

on a repeated, intermittent basis, (1) obtaining the test data from the memory device using the information, (2) testing the test data, (3) incrementally adjusting the current value in response to drift detected relative to the current value, to thereby define a new value, and (4) applying the new value in the storage for ensuing use as the current value.

20. The method of claim 19, wherein:

the method further comprises performing (1)-(4) on a periodic basis;

the method further comprises transmitting write data from the memory controller IC to the memory device according to a transmit phase defined relative to a transmit clock;

the method further comprises

establishing an initial value of the transmit phase during a calibration operation; and

using circuitry to compensate for drift between the value of the transmit phase and timing associated with the write data received by the memory device, and to adjust the value of the transmit phase in response to drift detected subsequent to establishment of the initial value of the transmit phase;

wherein using the circuitry to compensate for drift between the value of the transmit phase and the timing associated with the write data includes transmitting second test data from the memory device via the communication channel, reading back and test the second test data, and incrementally adjusting the value of the transmit in order to maintain a predetermined phase relationship between the transmit clock and second test data transmitted to the memory device.