High performance IP processor using RDMA

• US 9,667,723 B2
• Filed: 03/02/2015
• Issued: 05/30/2017
• Est. Priority Date: 06/11/2002
• Status: Expired due to Term

• Current Assignee: Memory Access Technologies LLC
• Original Assignee: Ashish A. Pandya
• Inventors: Pandya, Ashish A.
• Primary Examiner(s): Dalencourt, Yves
• Application Number:
  US14/635,807
• Publication Number:
  US 20150222706A1
• Time in Patent Office: 820 Days
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.

Claims

1. A method of using a hardware-implemented processor for enabling storage or retrieval of data in a memory subsystem, in a target system comprising a host processor and coupled to a TCP/IP network consisting of TCP/IP protocol and comprising a transport layer and a network layer wherein the transport layer and network layer consist of TCP/IP, the method comprising:

(a) receiving a request to register a region of memory from an application running on the target system;

(b) making the region of memory available to one or more peers of the application running on the target system that made the request;

(c) receiving data packets, by the hardware-implemented processor, via the network consisting of TCP/IP, at the target system;

(d) receiving a remote direct memory access request in the data packets transmitted via the network consisting of TCP/IP, the remote direct memory access request including a location of a region of memory registered for the remote direct access memory operation;

(e) in response to the receiving acts in parts (c) and (d), storing data to or retrieving data from the memory subsystem with the hardware-implemented processor, without the host processor controlling memory access during the storing or retrieving; and

(f) wherein the remote direct memory access request specifies the data stored or retrieved.

2. The method of claim 1 further comprising:

(i) registering a region of the memory subsystem of the target system for access by a remote initiator system coupled to the TCP/IP network;

(ii) directing a message to the remote initiator system identifying the registered region of the memory subsystem;

(iii) receiving additional remote direct memory access requests from the remote initiator system; and

(iv) transferring data specified by the additional remote direct memory access requests to or from the registered region of the memory subsystem with the hardware-implemented processor without the host processor controlling the transferring of data.

3. The method of claim 2 wherein the registering comprises registering the identity of the region of the memory subsystem with the initiator system.

4. The method of claim 2 wherein the registered region of the memory subsystem comprises a buffer.

5. The method of claim 2 further comprising, in response to the additional remote direct memory access requests received from the initiator system, using the host processor in the target system to:

(A) perform address translation of memory addresses;

(B) compare the translated addresses to the registered region;

(C) perform security key verification; and

(D) if the comparing and the verification are successful, allow the hardware-implemented processor to store the data to or retrieve the data from the translated memory addresses without the host processor controlling the storage or retrieval of the data.

6. The method of claim 2 further comprising, in response to the additional remote direct memory access requests received from the initiator system:

(A) using the host processor in the target system to perform address translation of memory addresses;

(B) comparing the translated addresses to the registered region;

(C) using the hardware-implemented processor to perform security key verification; and

(D) if the comparing and the verification are successful, allowing the hardware-implemented processor to store the data to or retrieve the data from the specified memory addresses without the host processor controlling the storage or retrieval of the data.

7. The method of claim 2 further comprising, in response to the additional remote direct memory access requests received from the initiator system, using the hardware-implemented processor to:

(A) perform address translation of memory addresses;

(B) compare the translated addresses to the registered region;

(C) perform security key verification; and

(D) if the comparing and the verification are successful, store the data to or retrieve the data from the specified memory addresses without the host processor controlling the storage or retrieval of the data.

8. The method of claim 2 further comprising, in response to the additional remote direct memory access requests received from the initiator system:

(A) using the hardware-implemented processor to perform address translation of memory addresses;

(B) comparing the translated addresses to the registered region;

(C) using the host processor in the target system to perform security key verification; and

(D) if the comparing and the verification are successful, allowing the hardware-implemented processor to store the data to or retrieve the data from the translated memory addresses without the host processor controlling the storage or retrieval of the data.