Single chip set-top box system

• US 9,668,011 B2
• Filed: 10/02/2001
• Issued: 05/30/2017
• Est. Priority Date: 02/05/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Cheung, Francis, D'Luna, Lionel
• Primary Examiner(s): Smith, Chenea
• Application Number:
  US99/692,12
• Time in Patent Office: 5,719 Days
• Field of Search: 725131
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/28 for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: H04B 1/66 for reducing bandwidth of signals; for improving efficiency of transmission H04B1/68 takes precedence
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42615 involving specific demultiplexing arrangements
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/435 Processing of additional data, e.g. decrypting of additional data, reconstructing software from modules extracted from the transport stream
• CPC Class Codes: H04N 21/4381 Recovering the multiplex stream from a specific network, e.g. recovering MPEG packets from ATM cells transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/8146 involving graphical data, e.g. 3D object, 2D graphics
• CPC Class Codes: H04N 5/44504 Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/602 : for digital sound signals
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

A single chip set-top box system and method is provided. The system comprises, for example, a transceiver, an audio/video decoder, a CPU, peripherals, DAVIC MAC and a graphics processor. The transceiver receives a digitally modulated compressed audio/video signal, and the audio/video decoder receives the compressed audio/video signal from the transceiver and decompresses the compressed audio/video signal. The graphics processor blends the decompressed audio/video signal with graphics to generate a blended video image with audio.

Claims

1. A single chip set-top box system comprising:

a transceiver operable to receive a digitally modulated compressed video signal from an in-band media stream and to demodulate the digitally modulated compressed video signal to generate a compressed video signal, wherein the compressed video signal carries a plurality of programs;

the transceiver further operable to receive an out-of-band media stream comprising graphics;

a transport processor operable to receive the compressed video signal and the graphics from the transceiver, wherein the transport processor comprises a filter configured to filter a portion of the compressed video signal corresponding to a particular one of the plurality of programs;

a video decoder operable to receive the portion of the compressed video signal from the transport processor and to decompress the portion of the compressed video signal;

a graphics processor operable to blend the decompressed portion of the video signal from the in-band media stream with the graphics from the out-of-band media stream to generate a blended video image, the graphics processor further being configured to adjust a pixel aspect ratio of the graphics to match a pixel aspect ratio of the video signal without affecting the pixel aspect ratio of the video signal; and

an analog video decoder operable to receive an analog video signal, to digitize the analog video signal, and to transmit the digitized analog video signal to the graphics processor to be blended with the decompressed portion of the video signal and the graphics,

wherein the transceiver, the transport processor, the video decoder, the graphics processor, and the analog video decoder are integrated on a single integrated circuit chip.

2. The single chip set-top box system according to claim 1 further comprising a DAVIC MAC, wherein the transceiver receives out-of-band data from the out-of-band media stream and provides the out-of-band data to the DAVIC MAC.

3. The single chip set-top box system according to claim 1 further comprising a central processing unit (CPU) operable to coordinate interfaces and activities of the transceiver, the video decoder, and the graphics processor, and wherein the filter filters the portion of the video signal corresponding to the particular one of the plurality of programs by examining program identifiers (PID).

4. The single chip set-top box system according to claim 1 further comprising a memory controller operable to control memory access of the transceiver, the video decoder, and the graphics processor in a unified memory system.

5. The single chip set-top box system according to claim 1 further comprising a video encoder operable to receive the blended video image from the graphics processor and to format the blended video image for display on a display device.

6. A multi-media system comprising:

a single integrated circuit comprising;

a transceiver operable to receive a digitally modulated compressed video signal from an in-band media stream and to demodulate the digitally modulated compressed video signal to generate a compressed video signal;

the transceiver further operable to receive an out-of-band media stream comprising graphics;

a video decoder operable to receive the compressed video signal from the transceiver and to decompress the compressed video signal;

a graphics processor operable to blend the graphics with the video signal, wherein the graphics processor is configured to adjust a pixel aspect ratio of the graphics from the out-of-band media stream to match a pixel aspect ratio of the video signal from the in-band media stream without affecting the pixel aspect ratio of the video signal;

a memory controller operable to arbitrate memory accesses of the transceiver, the video decoder, and the graphics processor to an off-chip shared single module memory;

a processor operable to coordinate interfaces and activities of the transceiver, the video decoder, and the graphics processor; and

an analog video decoder operable to receive an analog video signal, to digitize the analog video signal, and to transmit the digitized analog video signal to the graphics processor to be blended with the decompressed video signal and the graphics.

7. The multi-media system of claim 6, wherein the transceiver comprises a wireless transceiver.

8. The multi-media system of claim 6, wherein the transceiver comprises an ITU-T J.83 transceiver.

9. The multi-media system of claim 6, wherein the transceiver comprises a QAM receiver operable to receive the in-band media stream.

10. The multi-media system of claim 6, wherein the transceiver comprises a QPSK receiver operable to receive the out-of-band media stream.

11. The multi-media system of claim 6, wherein the transceiver comprises a QPSK/16-QAM transmitter.

12. The multi-media system of claim 6, wherein the processor comprises a central processing unit.

13. The multi-media system of claim 12, wherein the central processing unit comprises a MIPS.

14. The multi-media system of claim 6, wherein the single integrated circuit further comprises a MAC.

15. The multi-media system of claim 6, wherein the single integrated circuit further comprises an encoder that encodes at least one of audio and video, and wherein the memory controller arbitrates accesses of the encoder to the shared single module memory.

16. The multi-media system of claim 6, wherein the graphics of the out-of-band media stream are alpha blended with the decompressed video signal of the in-band media stream and an audio signal to generate a blended video image with sound.

17. The multi-media system of claim 6, wherein the compressed video signal is compressed in accordance with an MPEG standard.

18. The multi-media system of claim 17, wherein the MPEG standard comprises MPEG-1.

19. The multi-media system of claim 17, wherein the MPEG standard comprises MPEG-2.

20. The multi-media system of claim 17, wherein the MPEG standard comprises MPEG-4.

21. The multi-media system of claim 6, wherein the single integrated circuit further comprises a video encoder operable to receive a blended video image from the graphics processor and to format a blended video image for display on a display device, and wherein the memory controller also arbitrates accesses by the video encoder to the shared single module memory.

22. The multi-media system of claim 6, wherein the memory controller also arbitrates accesses by the analog video decoder to the shared single module memory.

23. The multi-media system of claim 6, wherein the single integrated circuit further comprises peripheral interfaces for user control of the multi-media system, and wherein the memory controller also arbitrates access by the peripheral interfaces to the shared single module memory.

24. The multi-media system of claim 6, further comprising the shared single module memory configured to store information during at least one of audio, video, data, or graphics processing.

25. The multi-media system of claim 6, wherein the single integrated circuit comprises at least one cache memory for storing instructions for execution by the processor.

26. The multi-media system of claim 25, wherein the processor comprises the at least one cache memory.

27. The multi-media system of claim 6, wherein the single integrated circuit comprises memory configured to be a buffer for system memory.

28. The multi-media system of claim 6, wherein the video decoder further comprises an audio decoder.

29. The multi-media system of claim 28, wherein the audio decoder is implemented as a plurality of hard-wired processing functions.

30. The multi-media system of claim 28, wherein the audio decoder is implemented as firmware.

31. The multi-media system of claim 30, wherein the audio decoder comprises a programmable ASIC.

32. The multi-media system of claim 28, wherein the audio decoder is implemented as software.

33. The multi-media system of claim 32, wherein the audio decoder is programmed in the processor.

34. The multi-media system of claim 28, wherein the audio decoder comprises an audio decompression processor.

35. The multi-media system of claim 34, wherein the audio decompression processor comprises a plurality of modules.

36. The multi-media system of claim 6, wherein the graphics processor is implemented in hardware.

37. The multi-media system of claim 6, wherein the graphics processor is implemented in firmware.

38. The multi-media system of claim 37, wherein the graphics processor comprises a programmable ASIC.

39. The multi-media system of claim 6, wherein the graphics processor is implemented as software.

40. The multi-media system of claim 6, wherein the graphics processor is implemented as at least two of hardware, firmware, or software.

41. The multi-media system of claim 6, wherein the memory controller supplies data to an upstream transmitter, and also arbitrates a request for said data from the shared single module memory.

42. The multi-media system of claim 41, wherein the memory controller supplies the data from a memory on the single integrated circuit.

43. The multi-media system of claim 42, wherein the data is stored in the memory by the processor.

44. The multi-media system of claim 6, wherein the single integrated circuit further comprises a DAVIC MAC.

45. The multi-media system of claim 44, wherein the DAVIC MACsupplies an upstream transmitter with serialized data from the shared single module memory to the single integrated circuit, and wherein the memory controller also arbitrates accesses by the DAVIC MAC to the shared single module memory.

46. The multi-media system of claim 6, wherein the memory controller supports message transfer from at least one buffer to the shared single module memory.

47. The multi-media system of claim 6, wherein the memory controller supports message transfer from a plurality of message buffers.

48. The multi-media system of claim 6, wherein the memory controller supports message transfer to a unified system memory external to the single integrated circuit.

49. A multi-media system comprising:

a transceiver operable to receive a digitally modulated compressed video signal from an in-band media stream and to demodulate the digitally modulated compressed video signal to generate a compressed video signal;

the transceiver further operable to receive an out-of-band media stream comprising graphics;

a video decoder operable to receive the compressed video signal from the transceiver and to decompress the compressed video signal;

a graphics processor operable to blend the graphics with the video signal, wherein the graphics processor is configured to adjust a pixel aspect ratio of the graphics to match a pixel aspect ratio of the video signal without affecting the pixel aspect ratio of the video signal;

an analog video decoder operable to receive an analog video signal, to digitize the analog video signal, and to transmit the digitized analog video signal to the graphics processor to be alpha blended with the decompressed video signal and the graphics;

a processor that at least assists in coordination of operation of the transceiver, the video decoder, and the graphics processor, wherein said transceiver, said video decoder, said graphics processor, said processor, and said analog video decoder are all integrated on a single chip; and

a memory controller operable to control accesses by an audio decoder, the video decoder, and the graphics processor to an off-chip shared single module memory.

50. The multi-media system of claim 49, wherein the transceiver comprises a wireless transceiver.

51. The multi-media system of claim 49, wherein the transceiver comprises an ITU-T J.83 transceiver.

52. The multi-media system of claim 49, wherein the transceiver comprises a QAM receiver operable to receive the in-band media stream comprising the video signal.

53. The multi-media system of claim 49, wherein the transceiver comprises a QPSK receiver operable to receive the out-of-band media stream comprising the graphics.

54. The multi-media system of claim 49, wherein the transceiver comprises a QPSK/16-QAM transmitter.

55. The multi-media system of claim 49, wherein the processor comprises a central processing unit.

56. The multi-media system of claim 55, wherein the central processing unit comprises a MIPS.

57. The multi-media system of claim 49 further comprising a MAC integrated on the single chip.

58. The multi-media system of claim 49, further comprising an encoder integrated on the single chip, and wherein the encoder encodes at least one of audio or video, and wherein the memory controller also arbitrates access to the shared single module memory by the encoder.

59. The multi-media system of claim 49, wherein the graphics are blended with the decompressed video signal and an audio signal to generate a blended video image with sound.

60. The multi-media system of claim 49, wherein the compressed video signal is compressed in accordance with an MPEG standard.

61. The multi-media system of claim 60, wherein the MPEG standard comprises MPEG-1.

62. The multi-media system of claim 60, wherein the MPEG standard comprises MPEG-2.

63. The multi-media system of claim 60, wherein the MPEG standard comprises MPEG-4.

64. The multi-media system of claim 49 further comprising a video encoder integrated on the single chip, and wherein the video encoder receives a blended video image from the graphics processor and formats a blended video image for display on a display device, and wherein the memory controller arbitrates access to the shared single module memory by the video encoder.

65. The multi-media system of claim 49, wherein the memory controller arbitrates access to the shared single module memory by the analog video decoder.

66. The multi-media system of claim 49 further comprising peripheral interfaces integrated on the single chip, and wherein the peripheral interfaces provide for user control of the multi-media system.

67. The multi-media system of claim 49 further comprising system memory external to the single chip and configured to store information during at least one of audio, video, data, or graphics processing.

68. The multi-media system of claim 49 comprising at least one cache memory integrated on the single chip.

69. The multi-media system of claim 68, wherein the processor comprises the cache memory.

70. The multi-media system of claim 67 comprising memory integrated on the single chip and configured to be a buffer for the system memory.

71. The multi-media system of claim 49, wherein the video decoder further comprises an audio decoder.

72. The multi-media system of claim 71, wherein the audio decoder is implemented as a plurality of hard-wired processing functions.

73. The multi-media system of claim 71, wherein the audio decoder is implemented as firmware.

74. The multi-media system of claim 73, wherein the audio decoder comprises a programmable ASIC.

75. The multi-media system of claim 71, wherein the audio decoder is implemented as software.

76. The multi-media system of claim 75, wherein the audio decoder is programmed in the processor.

77. The multi-media system of claim 71, wherein the audio decoder comprises an audio decompression processor.

78. The multi-media system of claim 77, wherein the audio decompression processor comprises a plurality of modules.

79. The multi-media system of claim 49, wherein the graphics processor is implemented in hardware.

80. The multi-media system of claim 49, wherein the graphics processor is implemented in firmware.

81. The multi-media system of claim 80, wherein the graphics processor comprises a programmable ASIC.

82. The multi-media system of claim 49, wherein the graphics processor is implemented as software.

83. The multi-media system of claim 49, wherein the graphics processor is implemented as at least two of hardware, firmware, or software.

84. The multi-media system of claim 49, wherein the memory controller supplies data to an upstream transmitter, and also arbitrates access to the data from the shared single module memory by the upstream transmitter.

85. The multi-media system of claim 49, wherein the single chip further comprises a DAVIC MAC, and wherein the memory controller also arbitrates accesses to the shared single module memory by the DAVIC MAC.

86. The multi-media system of claim 85, wherein the DAVIC MAC supplies an upstream transmitter with serialized data from a system memory external to the single chip.

87. The multi-media system of claim 84, wherein the memory controller supports message transfer from at least one buffer to memory.

88. The multi-media system of claim 84, wherein the memory controller supports message transfer from a plurality of message buffers.

89. The multi-media system of claim 84, wherein the memory controller supports message transfer to a system memory external to the single chip.