3D IC testing apparatus

• US 9,671,457 B2
• Filed: 12/05/2014
• Issued: 06/06/2017
• Est. Priority Date: 05/11/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hao, Wang, Mill-Jer, Peng, Ching-Nen, Lin, Hung-Chih, Chen, Chih-Chia
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US14/561,442
• Publication Number:
  US 20150087089A1
• Time in Patent Office: 914 Days
• Field of Search: None
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: Y02P 80/30 Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.

Claims

1. A method comprising:

connecting a testing setup having a plurality of probes to a device under test having a plurality of vias in a first substrate, wherein a probe is aligned with a corresponding via of the device under test, the first substrate being electrically coupled to a semiconductor die using micro bumps, the semiconductor die having a conductive element; and

conducting a plurality of via electrical characteristic tests through a conductive path comprising the plurality of vias, the probes, the semiconductor die and the conductive element, the conductive element electrically coupling two adjacent probes, wherein the first substrate is stacked on a first side of the semiconductor die, and wherein the conductive element is on a second side of the semiconductor die.

2. The method of claim 1, further comprising:

connecting a first terminal of a first probe to a first terminal of a first via through a first flip chip bump; and

connecting a first terminal of a second probe to a first terminal of a second via through a second flip chip bump, wherein a first conductive device is coupled between a second terminal of the first probe and a second terminal of the second probe, wherein the first conductive device is in the testing setup.

3. The method of claim 2, further comprising:

a third via; and

a dummy die coupled between the second via and the third via, wherein an external connection device is formed on the dummy die and electrically connects the second via with the third via.

4. The method of claim 3, wherein:

the first via, the first probe, the first conductive device, the second probe, the second via, the external connection device and the third via form a conductive chain.

5. The method of claim 1, wherein:

the testing setup is an automatic testing equipment (ATE) board.

6. The method of claim 1, further comprising:

connecting the testing setup with the device under test having the plurality of vias, wherein the device under test comprises an interposer and a dummy die, and wherein the vias are in the interposer and an external connection device is on the dummy die, and wherein the external connection device connects two adjacent vias.

7. The method of claim 1, further comprising:

connecting the testing setup with the device under test having the plurality of vias, wherein the device under test comprises a plurality of 3D IC dies, and wherein the vias are in a first 3D IC die and an external connection device is on a second 3D IC die, and wherein the first 3D IC die is connected with the second 3D IC die through a plurality of micro bumps.

8. A method comprising:

providing a device under test comprising a plurality of through vias and a connection device coupled between two adjacent through vias;

connecting a testing setup having a plurality of probes to the device under test, wherein a probe is aligned with a corresponding via of the device under test and the testing setup comprises a plurality of conductive devices, each of which connects two adjacent probes;

forming a conductive chain comprising the plurality of through vias of the device under test, the probes, the connection device, a first micro bump, a second micro bump and the plurality of conductive devices as a result of connecting the testing setup having a plurality of probes to the device under test, wherein the first micro bump and the second micro bump are between and in contact with the plurality of through vias of the device under test and a first side of a semiconductor die, and wherein the connection device is on a second side of the semiconductor die and connected to the first micro bump and the second micro bump through connecting elements embedded in the semiconductor die; and

conducting a plurality of via electrical characteristic tests through the conductive chain.

9. The method of claim 8, further comprising:

forming the conductive chain through a removable contact between the probes and the device under test.

10. The method of claim 8, further comprising:

conducting resistance, capacitance and leakage current tests of the plurality of through vias through the conductive chain.

11. The method of claim 8, wherein the device under test comprises an interposer and a dummy die, and wherein:

the vias are in the interposer and the connection device is on the dummy die, and wherein the connection device connects two adjacent vias through first connecting elements embedded in the dummy die, and second connecting elements between the interposer and the dummy die.

12. The method of claim 8, wherein the device under test comprises a plurality of 3D IC dies, and wherein:

the vias are in a first 3D IC die and the connection device is on a second 3D IC die, and wherein the first 3D IC die is connected with the second 3D IC die through a plurality of micro bumps between the first 3D IC die and the second 3D IC die, and third connecting elements embedded in the second 3D IC die.

13. A method comprising:

providing a plurality of connection devices formed in a testing apparatus; and

forming a through silicon via (TSV) chain by coupling a plurality of TSVs in a device under test (DUT) with the plurality of connection devices, wherein the TSV chain comprises a first micro bump between and in contact with a first via of the plurality of TSVs and a first side of a semiconductor die, and a second micro bump between and in contact with a second via of the plurality of TSVs and the first side of the semiconductor die, and wherein at least one conductive element is on a second side of the semiconductor die and directly connects two vias of the semiconductor die.

14. The method of claim 13, further comprising:

providing a plurality of dummy dies having a plurality of conductive elements coupled to one side of the DUT; and

forming the TSV chain by coupling the plurality of TSVs in the DUT with the plurality of connection devices in the testing apparatus and the plurality of conductive elements in the dummy dies.

15. The method of claim 13, further comprising:

generating a testing signal at a first terminal of the TSV chain; and

receiving a result signal at a second terminal of the TSV chain, wherein the result signal comprises electrical characteristics of the plurality of TSVs.

16. The method of claim 13, further comprising:

stacking a plurality of 3D dies to form a 3D device;

connecting a plurality of TSV terminals on a top side of the 3D device with the plurality of connection devices formed in the testing apparatus; and

connecting a plurality of TSV terminals on a bottom side of the 3D device with a plurality of connection paths formed on the bottom side of the 3D device.

17. The method of claim 13, wherein the DUT is an interposer having a first side coupled to the testing apparatus and a second side coupled to a plurality of dummy dies.

18. The method of claim 13, wherein the DUT is an interposer having a first side coupled to the testing apparatus and a second side having a plurality of connection elements, wherein each of the connection elements connects two adjacent terminals of a TSV.