Memory system and read reclaim method thereof

• US 9,672,104 B2
• Filed: 05/17/2016
• Issued: 06/06/2017
• Est. Priority Date: 10/05/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hwan-Chung, Park, Kyoungkuy, Park, Eunju, Jung, Young Woo, Seol, Bong-Gwan
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): ROCHE, JOHN B
• Application Number:
  US15/156,912
• Publication Number:
  US 20160259685A1
• Time in Patent Office: 385 Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation. The read reclaim operation is processed as complete when all the valid data of the target memory block is transferred to the one or more memory blocks of the first memory area.

Claims

1. A memory system comprising:

a nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store 3-bit data, each of the plurality of second memory cells being configured to store 1-bit data; and

a controller configured to control the nonvolatile memory device to perform a read operation, a program operation and a re-program operation, wherein;

the controller is configured to perform an error checking and correction (ECC) operation on first data to generate ECC-performed first data, the first data being read from a first portion of the plurality of first memory cells at a first voltage level,

the controller is configured to perform a read retry operation and the ECC operation on second data to generate ECC-performed second data when a number of error bits of the ECC-performed first data exceeds a threshold correctable by the ECC operation, the read retry operation including reading the second data stored in the first portion of the plurality of first memory cells at a second voltage level that is different from the first voltage level, the second data being read from the first portion of the plurality of first memory cells,

the controller is configured to output to the nonvolatile memory device first page data including either the ECC-performed first data or the ECC-performed second data,

the nonvolatile memory device is configured to program the first page data in a first portion of the plurality of second memory cells,

the nonvolatile memory device is configured to read the programmed first page data in the first portion of the plurality of second memory cells,

the nonvolatile memory device is configured to program in a second portion of the plurality of first memory cells the programmed first page data that is read at a first time from the first portion of the plurality of second memory cells, and

the nonvolatile memory device is configured to re-program in the second portion of the plurality of first memory cells the programmed first page data that is read at a second time from the first portion of the plurality of second memory cells.

2. The memory system of claim 1, wherein the first time is different from the second time.

3. The memory system of claim 1, wherein the controller is configured to program in the second portion of the plurality of first memory cells the first page data that is read at the first time from the first portion of the plurality of second memory cells, without performing the ECC operation on the first page data.

4. The memory system of claim 1, wherein the controller is configured to perform the read retry operation and the ECC operation on third data that is read from the first portion of the plurality of first memory cells.

5. The memory system of claim 1, wherein the controller is configured to perform the ECC operation on third data that is read from the second portion of the plurality of first memory cells.

6. The memory system of claim 5, wherein the first portion of the plurality of first memory cells and the second portion of the plurality of first memory cells are included in the same memory block.

7. The memory system of claim 5, wherein the third data is included in second page data that is output to the nonvolatile memory device from the controller.

8. The memory system of claim 7, wherein each of the first page data and the second page data is valid page data.

9. The memory system of claim 1, wherein the controller is configured to read and program the first page data in the first portion of the plurality of second memory cells after the controller processes a request by an external device.

10. The memory system of claim 7, wherein the first page data and the second page data are output to the nonvolatile memory device from the controller within a predetermined time period.

11. The memory system of claim 1, wherein the nonvolatile memory device includes a memory cell array having a vertical or stack-type three-dimensional array structure.

12. A memory system comprising:

a nonvolatile memory device including;

a first group of flash memory cells formed of a plurality of first memory blocks, each of the first group of flash memory cells being configured to store 1-bit data per cell; and

a second group of flash memory cells formed of a plurality of second memory blocks, each of the second group of flash memory cells being configured to store 3-bit data per cell; and

a memory controller configured to control the nonvolatile memory device, wherein;

the memory controller is configured to perform a read reclaim operation to transfer valid data stored in one of the plurality of second memory blocks to one or more memory blocks of the plurality of first memory blocks,

the read reclaim operation is performed on a first portion of the valid data at a first time, is performed on a second portion of the valid data at a second time that is different from the first time, and includes a read retry operation on at least a portion of the valid data,

the memory controller is configured to perform one or more program operations to transfer a third portion of the valid data that is read from the one or more memory blocks of the plurality of first memory blocks to another of the plurality of second memory blocks other than the one of the plurality of second memory blocks, and

each block of the first and second memory blocks constitutes the smallest erasable unit of flash memory cells within the nonvolatile memory device.

13. The memory system of claim 12, wherein the memory controller is configured to perform the one or more program operations to transfer the third portion of the valid data to the other plurality of second memory blocks, without performing an error checking and correction (ECC) operation on the third portion of the valid data.

14. The memory system of claim 12, wherein each of the one or more program operations is a three-step programming operation.

15. The memory system of claim 14, wherein:

the three-step programming operation includes a first program step and a second program step that occurs after the first program step, and

a second threshold voltage distribution corresponding to the second program step is narrower than a first threshold voltage distribution corresponding to the first program step.

16. The memory system of claim 12, wherein:

the read reclaim operation is performed during a first time period and a second time period, and

the first time period and the second time period are separated from each other.

17. The memory system of claim 12, wherein the nonvolatile memory device includes a memory cell array having a vertical or stack-type three-dimensional array structure.

18. A method of operating a nonvolatile memory system including a controller and a nonvolatile memory device, the nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store 3-bit data, each of the plurality of second memory cells being configured to store 1-bit data, the method executed by the controller and comprising:

reading, at a first voltage level, first data from a first portion of the plurality of first memory cells;

performing an error checking and correction (ECC) operation on the first data to generate ECC-performed first data;

reading, at a second voltage level, second data that is read from the first portion of the plurality of first memory cells when a number of error bits of the ECC-performed first data exceeds a threshold correctable by the ECC operation;

performing the ECC operation on the second data to generate ECC-performed second data;

outputting to the nonvolatile memory device first page data that includes either the ECC-performed first data or the ECC-performed second data;

programming the first page data in a first portion of the plurality of second memory cells;

reading the programmed first page data in the first portion of the plurality of second memory cells at a first time;

programming in a second portion of the plurality of first memory cells the programmed first page data that is read at the first time;

reading the programmed first page data in the first portion of the plurality of second memory cells at a second time; and

re-programming in the second portion of the plurality of first memory cells the programmed first page data that is read at the second time.

19. The method of claim 18, wherein the programming of the first page data in the second portion of the plurality of first memory cells is performed without the ECC operation on the first page data.

20. The method of claim 18, further comprising:

performing the ECC operation on third data that is read from a third portion of the plurality of first memory cells, the third data being included in second page data that is output to the nonvolatile memory device from the controller, and

the first page data and the second page data are output to the nonvolatile memory device from the controller within a predetermined time period.

21. The method of claim 20, wherein the first page data and the second page data are output to the nonvolatile memory device from the controller after the controller processes a request by an external device.

22. The method of claim 18, wherein the nonvolatile memory device includes a memory cell array having a vertical or stack-type three-dimensional array structure.

23. A memory system comprising:

a nonvolatile memory device including a plurality of first memory cells and a plurality of second memory cells, each of the plurality of first memory cells being configured to store 3-bit data, each of the plurality of second memory cells being configured to store 1-bit data, the nonvolatile memory device including a memory cell array having a vertical or stack-type three-dimensional array structure; and

a controller configured to control the nonvolatile memory device to perform a read operation, a program operation and a re-program operation, wherein;

the controller is configured to perform an error checking and correction (ECC) operation on first data to generate ECC-performed first data, the first data being read from a first portion of the plurality of first memory cells at a first voltage level,

the controller is configured to perform a read retry operation and the ECC operation on second data to generate ECC-performed second data when a number of error bits of the ECC-performed first data exceeds a threshold correctable by the ECC operation, the read retry operation including reading the second data stored in the first portion of the plurality of first memory cells at a second voltage level that is different from the first voltage level, the second data being read from the first portion of the plurality of first memory cells,

the controller is configured to output to the nonvolatile memory device first page data including either the ECC-performed first data or the ECC-performed second data,

the nonvolatile memory device is configured to program the first page data in a first portion of the plurality of second memory cells,

the nonvolatile memory device is configured to read the programmed first page data in the first portion of the plurality of second memory cells,

the nonvolatile memory device is configured to program in a second portion of the plurality of first memory cells the programmed first page data that is read at a first time from the first portion of the plurality of second memory cells,

the nonvolatile memory device is configured to re-program in the second portion of the plurality of first memory cells the programmed first page data that is read at a second time from the first portion of the plurality of second memory cells, and

the first time is different from the second time.

24. The memory system of claim 23, wherein the controller is configured to program in the second portion of the plurality of first memory cells the first page data that is read at the first time from the first portion of the plurality of second memory cells, without performing the ECC operation on the first page data.

25. The memory system of claim 23, wherein the controller is configured to perform the read retry operation and the ECC operation on third data that is read from the first portion of the plurality of first memory cells.

26. The memory system of claim 23, wherein the controller is configured to perform the ECC operation on third data that is read from the second portion of the plurality of first memory cells.

27. The memory system of claim 26, wherein the first portion of the plurality of first memory cells and the second portion of the plurality of first memory cells are included in the same memory block.

28. The memory system of claim 26, wherein the third data is included in second page data that is output to the nonvolatile memory device from the controller.

29. The memory system of claim 28, wherein each of the first page data and the second page data is valid page data.