Method and device for storing data in a memory, corresponding apparatus and computer program product

• US 9,672,155 B2
• Filed: 03/20/2015
• Issued: 06/06/2017
• Est. Priority Date: 07/08/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Leo, Marco, Rosingana, Paolo, Castellano, Marco
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US14/664,630
• Publication Number:
  US 20160011981A1
• Time in Patent Office: 809 Days
• Field of Search: 711132
• CPC Class Codes: G01D 9/005 Solid-state data loggers
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/451 Stack data

Abstract

A plurality of sensors provide respective output data rates, with a first sensor that has a highest output data rate, while one or more other sensors have output data rates that are submultiples of the aforesaid highest output data rate. The data signals coming from the sensors are stored in a memory, e.g., a FIFO memory, by storing the data signals of the first sensor at the aforesaid highest output data rate, accompanying storage of the data signals coming from said first sensor with storage of the data signals coming from the sensors as supplied by said other sensors at the aforesaid submultiple output data rates, so that the data signals are stored in the memory according to a repeated pattern that is common to the various sensors.

Claims

1. A system including:

a memory configured to store data signals provided by a plurality of sensors at respective output data rates, wherein a first sensor in said plurality has a highest output data rate and one or more other sensors in said plurality have output data rates that are sub-multiple of said highest output data rate, and

a processor coupled to said memory and configured to store in the memory data signals provided by a plurality of sensors at respective output data rates, wherein a first sensor in said plurality has a highest output data rate while one or more other sensors in that plurality have output data rates that are sub-multiples of said highest output data rate, including storing in said memory the data signals from said first sensor at said highest data rate by accompanying storing of the data signals from said first sensor with storing the data signals from said one or more other sensors as provided by said one or more other sensors at said sub-multiple output data rates, whereby said data signals are stored in said memory in a repeated pattern common to said plurality of sensors.

2. The system of claim 1, wherein said repeated common pattern is an indexed pattern including first indexed entries for storing events taking place at said highest data rate and second indexed entries indicative of which data signals from which sensors of said plurality are stored in the memory at each of a plurality of storing events.

3. The system of claim 2, wherein said indexed pattern is a matrix pattern that includes rows indicative of storing events taking place at said highest data rate and locations in said rows are indicative of which data signals from which sensors of said plurality are stored in the memory at each of said plurality of storing events.

4. The system of claim 2, wherein the processor is configured to retrieve data signals from said memory using a pointer pointing to said first and second indexed entries.

5. The system of claim 1, wherein the processor is configured to:

detect a full condition of said memory, and at least one of;

raise a flag to prevent overwriting of data signals in the memory in response to detecting said full condition of said memory, and

permit overwriting of data in said memory on an axis-by-axis basis, wherein said data signals from said sensors include data signal components related to plural detection axes.

6. An apparatus comprising:

a plurality of sensors configured to provide data signals at respective output data rates, wherein a first sensor in said plurality has a highest output data rate while one or more other sensors in said plurality have output data rates that are sub-multiples of said highest output data rate,

a memory configured to store data signals provided by a plurality of sensors at respective output data rates, wherein a first sensor in said plurality has a highest output data rate and one or more other sensors in said plurality have output data rates that are sub-multiple of said highest output data rate, and

a processor coupled to said memory and configured to store in the memory data signals provided by a plurality of sensors at respective output data rates, wherein a first sensor in said plurality has a highest output data rate while one or more other sensors in that plurality have output data rates that are sub-multiples of said highest output data rate, including storing in said memory the data signals from said first sensor at said highest data rate by accompanying storing of the data signals from said first sensor with storing the data signals from said one or more other sensors as provided by said one or more other sensors at said sub-multiple output data rates, whereby said data signals are stored in said memory in a repeated pattern common to said plurality of sensors.

7. The apparatus of claim 6, wherein said repeated common pattern is an indexed pattern including first indexed entries for storing events taking place at said highest data rate and second indexed entries indicative of which data signals from which sensors of said plurality are stored in the memory at each of a plurality of storing events.

8. The apparatus of claim 7, wherein said indexed pattern is a matrix pattern that includes rows indicative of storing events taking place at said highest data rate and locations in said rows are indicative of which data signals from which sensors of said plurality are stored in the memory at each of said plurality of storing events.

9. The apparatus of claim 7, wherein the processor is configured to retrieve data signals from said memory using a pointer pointing to said first and second indexed entries.

10. The apparatus of claim 6, wherein the processor is configured to:

detect a full condition of said memory, and at least one of;

raise a flag to prevent overwriting of data signals in the memory in response to detecting said full condition of said memory, and

permit overwriting of data in said memory on an axis-by-axis basis, wherein said data signals from said sensors include data signal components related to plural detection axes.

11. A method, comprising:

providing a processor;

providing a memory;

receiving data signals provided by a plurality of sensors at respective output data rates, wherein a first sensor in said plurality has a highest output data rate while one or more other sensors in that plurality have output data rates that are sub-multiples of said highest output data rate; and

executing instructions with the processor to direct storing the received data signals in the memory, the storing including storing in said memory the data signals from said first sensor at said highest data rate by accompanying storing of the data signals from said first sensor with storing the data signals from said one or more other sensors as provided by said one or more other sensors at said sub-multiple output data rates, whereby said data signals are stored in said memory in a repeated pattern common to said plurality of sensors.

12. The method of claim 11, wherein said repeated common pattern is an indexed pattern including first indexed entries for storing events taking place at said highest data rate and second indexed entries indicative of which data signals from which sensors of said plurality are stored in the memory at each of a plurality of storing events.

13. The method of claim 12, wherein said indexed pattern is a matrix pattern that includes rows indicative of storing events taking place at said highest data rate and locations in said rows are indicative of which data signals from which sensors of said plurality are stored in the memory at each of said plurality of storing events.

14. The method of claim 12, including retrieving data signals from said memory using a pointer pointing to said first and second indexed entries.

15. The method of claim 11, including detecting a full condition of said memory, wherein, upon said full condition of said memory being detected, the method includes at least one of:

raising a flag to prevent overwriting of data signals in the memory, and

wherein said data signals from said sensors include data signal components related to plural detection axes, permitting overwriting of data in said memory on an axis-by-axis basis.

16. The method of claim 11, including operating said memory as a first in-first out memory.

17. The method of claim 11, including operating said memory as a circular memory.

18. A non-transitive computer readable medium configured to cause at least one processor to implement a method comprising:

storing in a memory data signals provided by a plurality of sensors at respective output data rates, wherein a first sensor in said plurality has a highest output data rate while one or more other sensors in that plurality have output data rates that are sub-multiples of said highest output data rate,

the storing including storing in said memory the data signals from said first sensor at said highest data rate by accompanying storing of the data signals from said first sensor with storing the data signals from said one or more other sensors as provided by said one or more other sensors at said sub-multiple output data rates, whereby said data signals are stored in said memory in a repeated pattern common to said plurality of sensors.

19. The non-transitive computer readable medium of claim 18, wherein said repeated common pattern is an indexed pattern including first indexed entries for storing events taking place at said highest data rate and second indexed entries indicative of which data signals from which sensors of said plurality are stored in the memory at each of a plurality of storing events.

20. The non-transitive computer readable medium of claim 19, wherein said indexed pattern is a matrix pattern that includes rows indicative of storing events taking place at said highest data rate and locations in said rows are indicative of which data signals from which sensors of said plurality are stored in the memory at each of said plurality of storing events.