Data processing systems

• US 9,672,162 B2
• Filed: 08/16/2013
• Issued: 06/06/2017
• Est. Priority Date: 08/16/2013
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Persson, Hakan, Ellis, Sean Tristram
• Primary Examiner(s): Yi, David X
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US13/969,277
• Publication Number:
  US 20150052325A1
• Time in Patent Office: 1,390 Days
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 12/1458 by checking the subject access rights

Abstract

A data processing system includes a host processor and a graphics processing unit operable to process data under the control of an operating system executing on the host processor. The graphics processing unit can be switched between a normal mode of operation in which the it has read and write access to data that is stored in non-protected memory regions 9 but no or write-only access to any protected memory regions 8, and a protected mode of operation in which it has read and write access to data that is stored in protected memory regions 8 but only has read-only access to any non-protected memory regions 9. The data processing system further comprises a mechanism for switching the graphics processing unit from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

Claims

1. A data processing system, the data processing system comprising:

a host processor that executes an operating system;

an accelerator operable to process data under the control of the operating system executing on the host processor;

and memory for storing data to be used or processed by or generated by the accelerator, the memory being configurable to have both protected memory regions that are not readable by the operating system when it is operating in a non-secure mode and non-protected memory regions that are readable by the operating system when it is operating in a non-secure mode;

wherein;

the accelerator can be switched between a normal mode of operation in which the accelerator has read and write access to data that is stored in non-protected memory regions but write-only access to any protected memory regions, and a protected mode of operation in which the accelerator has read and write access to data that is stored in protected memory regions but only has read-only access to any non-protected memory regions; and

the data processing system further comprises a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation;

wherein the accelerator'"'"'s access to the memory is controlled by using bus transaction filtering or by using memory address virtualisation mapping in a memory management unit (MMU), wherein MMU stage two page tables are used for both normal mode and protected mode operation and wherein the same MMU stage two page tables are used for both normal mode and protected mode operation, but the interpretation of the page table access permissions depends upon the mode an accelerator processing operation is being performed in.

2. The system of claim 1, wherein the accelerator comprises one of:

a graphics processing unit, an encryption accelerator, a video accelerator, a network interface, a digital signal processor (DSP), or audio hardware.

3. The system of claim 1, wherein the operating system when operating in a non-secure mode of operation has write access but no read access to protected memory regions.

4. The system of claim 1, wherein the data processing system includes a firewall between the accelerator and the memory that controls access by the accelerator to the memory.

5. The system of claim 1, wherein the mechanism for switching the accelerator from its protected mode of operation to the normal mode of operation clears any stored data from the protected operation when it switches the accelerator from its protected mode of operation to the normal mode of operation.

6. The system of claim 1, wherein the mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation comprises one of:

using trusted firmware to control the switching;

using open firmware in conjunction with trusted host software for the switching;

using trusted host software for the switching;

or using a hardware implemented switching mechanism.

7. The system of claim 1, wherein the mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation, comprises using a microcontroller associated with the accelerator to control the switching.

8. A method of operating a data processing system that comprises:

a host processor that executes an operating system;

an accelerator operable to process data under the control of the operating system executing on the host processor;

and memory for storing data to be used or processed by or generated by the accelerator, the memory being configurable to have both protected memory regions that are not readable by the operating system when it is operating in a non-secure mode and non-protected memory regions that are readable by the operating system when it is operating in a non-secure mode;

wherein;

the accelerator can be switched between a normal mode of operation in which it has read and write access to data that is stored in non-protected memory regions but write-only access to any protected memory regions, and a protected mode of operation in which the accelerator has read and write access to data that is stored in protected memory regions but only has read-only access to any non-protected memory regions;

the method comprising;

when it is desired to use the accelerator to perform protected processing of data;

switching the accelerator to its protected mode of operation;

the accelerator, whilst it is operating in its protected mode of operation, reading data from and writing data to protected regions of the memory, and reading data from, but not writing data to, non-protected regions of the memory;

and when the accelerator has completed its protected processing task, switching the accelerator back to its normal mode of operation;

wherein the method further comprises using bus transaction filtering or using memory address virtualisation mapping in a memory management unit (MMU) to control the accelerator'"'"'s access to the memory, wherein MMU stage two page tables are used for both normal mode and protected mode operation and wherein the same MMU stage two page tables are used for both normal mode and protected mode operation, but the interpretation of the page table access permissions depends upon the mode an accelerator processing operation is being performed in.

9. The method of claim 8, wherein the accelerator comprises one of:

a graphics processing unit, an encryption accelerator, a video accelerator, a network interface, a digital signal processor (DSP), or audio hardware.

10. The method of claim 8, wherein the operating system when operating in a non-secure mode of operation has write access but no read access to protected memory regions.

11. The method of claim 8, comprising using a firewall between the accelerator and the memory to control access by the accelerator to the memory.

12. The method of claim 8, comprising clearing any stored data from the protected operation when switching the accelerator from its protected mode of operation to the normal mode of operation.

13. The method of claim 8, wherein the mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation comprises one of:

using trusted firmware to control the switching;

using open firmware in conjunction with trusted host software for the switching;

using trusted host software for the switching;

or using a hardware implemented switching mechanism.

14. The method of claim 8, comprising using a microcontroller associated with the accelerator to control the switching of the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

15. A non-transient computer readable storage medium storing computer software code which when executing on a processor performs a method of operating a data processing system that comprises:

a host processor that executes an operating system;

an accelerator operable to process data under the control of the operating system executing on the host processor;

and memory for storing data to be used or processed by or generated by the accelerator, the memory being configurable to have both protected memory regions that are not accessible to the operating system when it is operating in a non-secure mode and non-protected memory regions that are accessible to the operating system when it is operating in a non-secure mode;

wherein;

the accelerator can be switched between a normal mode of operation in which it has read and write access to data that is stored in non-protected memory regions but write-only access to any protected memory regions, and a protected mode of operation in which the accelerator has read and write access to data that is stored in protected memory regions but only has read-only access to any non-protected memory regions;

the method comprising;

when it is desired to use the accelerator to perform protected processing of data;

switching the accelerator to its protected mode of operation;

the accelerator, whilst it is operating in its protected mode of operation, reading data from and writing data to protected regions of the memory, and reading data from, but not writing data to, non-protected regions of the memory;

and when the accelerator has completed its protected processing task, switching the accelerator back to its normal mode of operation;

wherein the method further comprises using bus transaction filtering or using memory address virtualisation mapping in a memory management unit (MMU) to control the accelerator'"'"'s access to the memory, wherein MMU stage two page tables are used for both normal mode and protected mode operation and wherein the same MMU stage two page tables are used for both normal mode and protected mode operation, but the interpretation of the page table access permissions depends upon the mode an accelerator processing operation is being performed in.