Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system

• US 9,672,178 B1
• Filed: 04/15/2015
• Issued: 06/06/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Ponce, Cyrill C., Fuentes, Marizonne O., Noble, Gianico G.
• Primary Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US14/687,700
• Time in Patent Office: 783 Days
• Field of Search: 710 22, 710308
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 13/37 using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0683 Plurality of storage devices

Abstract

In an embodiment of the invention, a method comprises: A method, comprising: issuing, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and issuing, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table. In another embodiment of the invention, an apparatus comprises: a Direct Memory Access (DMA) engine configured to issue an update request to a dependency table if the DMA engine has finished executing a first descriptor, and configured to issue a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table.

Claims

1. A method, comprising:

issuing, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and

issuing, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the selected subindex is in the dependency table;

wherein the dependency table is coupled to the DMA engine by a request channel and a monitoring channel;

wherein the dependency table is coupled to a processor by an access channel; and

wherein the dependency table, request channel, monitoring channel, and access channel provide a hardware-based data transfer completion notification mechanism between the processor and the DMA engine so that the processor is not rendered as a bottleneck in a system.

2. The method of claim 1, further comprising:

updating a subindex bit value in the dependency table in response to the update request.

3. The method of claim 1, wherein each of a plurality of DMA engines uses a corresponding one of a plurality of subindex updaters that update subindex bit values in the dependency table in response to update requests from the DMA engines.

4. The method of claim 1, further comprising:

selecting which of a plurality of subindex updates is granted to write to an index in the dependency table.

5. The method of claim 1, further comprising:

routing the monitoring request to a monitor request buffer; and

selecting a given monitor request in the monitor request buffer to be executed by a monitor request router.

6. The method of claim 5,

wherein selecting the given monitor request in the monitor request buffer comprises using an arbitrated algorithm if the monitor request buffer is partially filled with monitoring requests.

7. The method of claim 5,

wherein selecting the given monitor request in the monitor request buffer comprises using a round-robin algorithm if the monitor request buffer is full of monitoring requests.

8. The method of claim 1, wherein each of a plurality of DMA engines uses a corresponding one of a plurality of monitor request routers that execute monitor requests from the DMA engines.

9. The method of claim 1, further comprising:

routing a target subindex in an index from the dependency table to a corresponding monitor register and subsequently out to a corresponding bit in the monitoring channel.

10. An apparatus, comprising:

a Direct Memory Access (DMA) engine configured to issue an update request to a dependency table if the DMA engine has finished executing a first descriptor, and configured to issue a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the selected subindex is in the dependency table;

wherein the dependency table is coupled to the DMA engine by a request channel and a monitoring channel;

wherein the dependency table is coupled to a processor by an access channel; and

wherein the dependency table, request channel, monitoring channel, and access channel provide a hardware-based data transfer completion notification mechanism between the processor and the DMA engine so that the processor is not rendered as a bottleneck in a system.

11. The apparatus of claim 10, further comprising:

an update selector configured to update a subindex bit value in the dependency table in response to the update request.

12. The apparatus of claim 10, wherein each of a plurality of DMA engines uses a corresponding one of a plurality of subindex updaters that update subindex bit values in the dependency table in response to update requests from the DMA engines.

13. The apparatus of claim 10, further comprising:

an update selector configured to select which of a plurality of subindex updates is granted to write to an index in the dependency table.

14. The apparatus of claim 10, further comprising:

a request selector configured to route the monitoring request to a monitor request buffer; and

a monitor request selector configured to select a given monitor request in the monitor request buffer to be executed by a monitor request router.

15. The apparatus of claim 14,

wherein the monitor request selector selects the given monitor request in the monitor request buffer by using an arbitrated algorithm if the monitor request buffer is partially filled with monitoring requests.

16. The apparatus of claim 14,

wherein the monitor request selector selects the given monitor request in the monitor request buffer by using a round-robin algorithm if the monitor request buffer is full of monitoring requests.

17. The apparatus of claim 10, wherein each of a plurality of DMA engines uses a corresponding one of a plurality of monitor request routers that execute monitor requests from the DMA engines.

18. The apparatus of claim 10, further comprising:

a monitor request router configured to route a target subindex in an index from the dependency table to a corresponding monitor register and subsequently out to a corresponding bit in the monitoring channel.

19. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to;

issue, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and

issue, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the selected subindex is in the dependency table;

wherein the dependency table is coupled to the DMA engine by a request channel and a monitoring channel;

wherein the dependency table is coupled to a processor by an access channel; and

wherein the dependency table, request channel, monitoring channel, and access channel provide a hardware-based data transfer completion notification mechanism between the processor and the DMA engine so that the processor is not rendered as a bottleneck in a system.

20. The article of manufacture of claim 19, wherein the instructions are operable to further permit the apparatus to:

update a subindex bit value in the dependency table in response to the update request.