Precise excecution of versioned store instructions
First Claim
1. A processor configured to execute versioned store instructions of a first thread within a first mode of operation, wherein the first mode is a debugging mode in which retirement control circuitry included in the processor is configured to:
- retire, from an ordering unit, each versioned store instruction in the first thread only after a respective version comparison has been performed, wherein the comparison is between version information included in that versioned store instruction and version information stored at a target location of that versioned store instruction; and
suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction of the first thread until the oldest versioned store instruction has retired;
wherein the processor is further configured to execute versioned store instructions of a given thread within a second mode of operation, wherein the second mode is a disrupting mode in which;
the retirement control circuitry is configured to retire at least one outstanding versioned store instruction before a version comparison has been performed for the at least one outstanding versioned store instruction;
the processor is configured to perform the version comparison, between version information included in the at least one versioned store instruction and version information stored at a target location of the at least one versioned store instruction, subsequent to retirement of the at least one outstanding versioned store instruction; and
instructions younger than the at least one versioned store instruction are allowed to commit results to the architectural state of the processor before the version comparison has been performed.
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Accused Products
Abstract
Techniques for executing versioned memory access instructions. In one embodiment, a processor is configured to execute versioned store instructions of a first thread within a first mode of operation. In this embodiment, in the first mode of operation, the processor is configured to retire a versioned store instruction only after a version comparison has been performed for the versioned store instruction. In this embodiment the processor is configured to suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction until the oldest versioned store instruction has retired. In some embodiments, the processor is configured to execute versioned store instructions of a given thread within a second mode of operation, in which the processor is configured to retire outstanding versioned store instructions before a version comparison has been performed.
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Citations
17 Claims
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1. A processor configured to execute versioned store instructions of a first thread within a first mode of operation, wherein the first mode is a debugging mode in which retirement control circuitry included in the processor is configured to:
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retire, from an ordering unit, each versioned store instruction in the first thread only after a respective version comparison has been performed, wherein the comparison is between version information included in that versioned store instruction and version information stored at a target location of that versioned store instruction; and suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction of the first thread until the oldest versioned store instruction has retired; wherein the processor is further configured to execute versioned store instructions of a given thread within a second mode of operation, wherein the second mode is a disrupting mode in which; the retirement control circuitry is configured to retire at least one outstanding versioned store instruction before a version comparison has been performed for the at least one outstanding versioned store instruction; the processor is configured to perform the version comparison, between version information included in the at least one versioned store instruction and version information stored at a target location of the at least one versioned store instruction, subsequent to retirement of the at least one outstanding versioned store instruction; and instructions younger than the at least one versioned store instruction are allowed to commit results to the architectural state of the processor before the version comparison has been performed. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method, comprising:
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executing, by a load/store unit of a processor, versioned store instructions of a first thread within a first mode of operation, wherein the first mode is a debugging mode, including; retiring, by retirement control circuitry, each versioned store instruction in the first thread only after a respective version comparison has been performed, where the comparison is between version information included in that versioned store instruction and version information stored at a target location of that versioned store instruction; and suppressing, by the retirement control circuitry, retirement of instructions in the first thread that are younger than an oldest versioned store instruction of the first thread until the oldest versioned store instruction has retired; and executing, by the load store unit, versioned store instructions of a second thread within a second mode of operation, wherein the second mode is a disrupting mode, in which; the processor retires at least one outstanding versioned store instruction before a version comparison has been performed for the at least one outstanding versioned store instruction; the processor performs a version comparison, between version information included in the at least one versioned store instruction and version information stored at a target location of the at least one versioned store instruction, subsequent to retirement of the at least one outstanding versioned store instruction; and instructions younger than the versioned store instructions are allowed to commit results to the architectural state of the processor before the version comparison has been performed. - View Dependent Claims (8, 9, 10, 11, 12)
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13. An apparatus, comprising:
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a reorder buffer configured to maintain a program order of instructions and to retire instructions in program order; and a memory controller configured to compare version information for versioned store instructions with version information stored in cache or memory locations corresponding to the store instructions; wherein the apparatus is configured execute instructions of a first thread according to a first mode of operation in which the apparatus is configured to retire a versioned store instruction from the reorder buffer only after a version comparison for the versioned store instruction has been performed; and wherein the apparatus is configured to execute versioned store instructions of a second thread within a second mode of operation, in which the apparatus is configured to retire at least one outstanding versioned store instruction before a version comparison has been performed for the at least one outstanding versioned store instruction, in which the apparatus is configured to perform a version comparison for the at least one outstanding versioned store instruction subsequent to retirement of the at least one outstanding versioned store instruction, and in which instructions younger than the versioned store instructions are allowed to commit results to the architectural state of the apparatus before the version comparison has been performed. - View Dependent Claims (14, 15, 16, 17)
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Specification