Precise excecution of versioned store instructions

• US 9,672,298 B2
• Filed: 05/01/2014
• Issued: 06/06/2017
• Est. Priority Date: 05/01/2014
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Jordan, Paul J., Luttrell, Mark A., Radovic, Zoran, Smolens, Jared C., Golla, Robert T.
• Primary Examiner(s): Choi, Carol
• Application Number:
  US14/267,734
• Publication Number:
  US 20150317338A1
• Time in Patent Office: 1,132 Days
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 16/219 Managing data history or versioning querying versioned data G06F16/2474; querying temporal data G06F16/2477
• CPC Class Codes: G06F 16/24564 Applying rules; Deductive queries
• CPC Class Codes: G06F 16/90344 by using string matching techniques
• CPC Class Codes: G06F 16/951 Indexing; Web crawling techniques
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification

Abstract

Techniques for executing versioned memory access instructions. In one embodiment, a processor is configured to execute versioned store instructions of a first thread within a first mode of operation. In this embodiment, in the first mode of operation, the processor is configured to retire a versioned store instruction only after a version comparison has been performed for the versioned store instruction. In this embodiment the processor is configured to suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction until the oldest versioned store instruction has retired. In some embodiments, the processor is configured to execute versioned store instructions of a given thread within a second mode of operation, in which the processor is configured to retire outstanding versioned store instructions before a version comparison has been performed.

Claims

1. A processor configured to execute versioned store instructions of a first thread within a first mode of operation, wherein the first mode is a debugging mode in which retirement control circuitry included in the processor is configured to:

retire, from an ordering unit, each versioned store instruction in the first thread only after a respective version comparison has been performed, wherein the comparison is between version information included in that versioned store instruction and version information stored at a target location of that versioned store instruction; and

suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction of the first thread until the oldest versioned store instruction has retired;

wherein the processor is further configured to execute versioned store instructions of a given thread within a second mode of operation, wherein the second mode is a disrupting mode in which;

the retirement control circuitry is configured to retire at least one outstanding versioned store instruction before a version comparison has been performed for the at least one outstanding versioned store instruction;

the processor is configured to perform the version comparison, between version information included in the at least one versioned store instruction and version information stored at a target location of the at least one versioned store instruction, subsequent to retirement of the at least one outstanding versioned store instruction; and

instructions younger than the at least one versioned store instruction are allowed to commit results to the architectural state of the processor before the version comparison has been performed.

2. The processor of claim 1, wherein the processor is configured to execute versioned store instructions of a second thread within the second mode of operation concurrently with executing versioned store instructions of the first thread within the first mode of operation.

3. The processor of claim 1, wherein the processor is configured to operate within either the first mode or the second mode for a given thread based on a programmable indicator.

4. The processor of claim 1, wherein the processor is configured, in response to a failed version comparison for a given versioned store instruction when operating in the first mode, to maintain architectural state information for the first thread, wherein instructions younger than the given versioned store instruction did not modify the architectural state information.

5. The processor of claim 1, wherein the processor is configured, when operating within the first mode of operation, to perform a version comparison for only a versioned store instruction that is currently an oldest non-retired versioned store instruction of the first thread.

6. The processor of claim 1, wherein, for a given versioned store instruction, the processor is configured to:

compare version information associated with the versioned store instruction with version information stored in a cache or memory, wherein the version information stored in the cache or memory is associated with a memory object at a target location of the store instruction;

retire the versioned store instruction from an ordering unit of the processor; and

perform the versioned store instruction in a cache or memory, wherein the cache or memory is included in or coupled to the processor.

7. A method, comprising:

executing, by a load/store unit of a processor, versioned store instructions of a first thread within a first mode of operation, wherein the first mode is a debugging mode, including;

retiring, by retirement control circuitry, each versioned store instruction in the first thread only after a respective version comparison has been performed, where the comparison is between version information included in that versioned store instruction and version information stored at a target location of that versioned store instruction; and

suppressing, by the retirement control circuitry, retirement of instructions in the first thread that are younger than an oldest versioned store instruction of the first thread until the oldest versioned store instruction has retired; and

executing, by the load store unit, versioned store instructions of a second thread within a second mode of operation, wherein the second mode is a disrupting mode, in which;

the processor retires at least one outstanding versioned store instruction before a version comparison has been performed for the at least one outstanding versioned store instruction;

the processor performs a version comparison, between version information included in the at least one versioned store instruction and version information stored at a target location of the at least one versioned store instruction, subsequent to retirement of the at least one outstanding versioned store instruction; and

instructions younger than the versioned store instructions are allowed to commit results to the architectural state of the processor before the version comparison has been performed.

8. The method of claim 7, wherein the executing within the first mode of operation is performed in response to selection of the first mode of operation by an application.

9. The method of claim 7, further comprising:

maintaining architectural state information for the first thread, wherein the architectural state information is associated with a given versioned store instruction and wherein instructions younger than the given versioned store instruction do not modify the architectural state information until the given versioned store instruction has successfully completed version comparison.

10. The method of claim 7, wherein the executing includes allowing at most one versioned store instruction of the first thread to be in a phase of execution between beginning version comparison and performance in a cache or memory.

11. The method of claim 10, wherein the executing includes allowing multiple non-versioned store instructions of the first thread at a time to be in the phase of execution between beginning version comparison and performance in a cache or memory.

12. The method of claim 7, further comprising executing instructions within a third mode of operation, including retiring and performing versioned store instructions without performing version comparison.

13. An apparatus, comprising:

a reorder buffer configured to maintain a program order of instructions and to retire instructions in program order; and

a memory controller configured to compare version information for versioned store instructions with version information stored in cache or memory locations corresponding to the store instructions;

wherein the apparatus is configured execute instructions of a first thread according to a first mode of operation in which the apparatus is configured to retire a versioned store instruction from the reorder buffer only after a version comparison for the versioned store instruction has been performed; and

wherein the apparatus is configured to execute versioned store instructions of a second thread within a second mode of operation, in which the apparatus is configured to retire at least one outstanding versioned store instruction before a version comparison has been performed for the at least one outstanding versioned store instruction, in which the apparatus is configured to perform a version comparison for the at least one outstanding versioned store instruction subsequent to retirement of the at least one outstanding versioned store instruction, and in which instructions younger than the versioned store instructions are allowed to commit results to the architectural state of the apparatus before the version comparison has been performed.

14. The apparatus of claim 13, wherein the apparatus is configured to operate within the first or the second mode of operation based on an indication from an application running on the apparatus.

15. The apparatus of claim 13, further comprising:

a store queue configured to maintain store data and target addresses for store instructions during version comparison;

wherein the reorder buffer is configured to maintain program counter information for versioned store instructions until they are retired.

16. The apparatus of claim 13, wherein the apparatus is configured to initiate an exception that identifies the versioned store instruction in response to the versioned store instruction failing the version comparison.

17. The apparatus of claim 13, further comprising:

first and second buffers;

wherein the apparatus is configured to maintain store data for versioned store instructions in the first buffer until they are ready to proceed to version comparison, then send the store data to the second buffer; and

wherein the apparatus is configured to send at most one versioned store instruction to the second buffer at a time within the first mode of operation.