Secure processor and a program for a secure processor

• US 9,672,384 B2
• Filed: 11/27/2013
• Issued: 06/06/2017
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: Kamada, Jun, Goto, Seiji, Tamiya, Taiji
• Primary Examiner(s): RAHIM, MONJUR
• Application Number:
  US14/091,483
• Publication Number:
  US 20140089680A1
• Time in Patent Office: 1,287 Days
• Field of Search: 713190
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/53 by executing in a restricted environment, e.g. sandbox or secure virtual machine
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/70 Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Claims

1. A processor comprising:

a key memory circuit configured to store a key;

an instruction code memory circuit configured to store a first program in a non-rewritable format;

an authentication circuit configured to authenticate the first program by using the key and an electronic signature corresponding to the first program;

a secure core circuit configured to execute the first program which is authenticated by the authentication circuit, the key memory circuit being connected to the secure core circuit; and

a normal core circuit physically separated from the secure core circuit and configured to be booted in response to the execution of the first program by the secure core circuit, the normal core circuit being configured to execute a second program which is not authenticated by the authentication circuit after being booted, the key memory circuit not being connected to the normal core circuit.

2. The processor according to claim 1,

wherein the key is specific to the secure core circuit.

3. The processor according to claim 1,

wherein the instruction code memory circuit is configured to store the first program in an encrypted format.

4. The processor according to claim 1,

wherein the authentication circuit is configured to decrypt the electronic signature by using the key and to authenticate the first program when an obtained decryption result matches a result of an operation performed on the first program.

5. The processor according to claim 1,

wherein the normal core circuit is booted after the secure core circuit is booted.

6. The processor according to claim 1, comprising

an encryption processing circuit configured to encrypt a target instruction code which is included in the first program and authenticated by the authentication circuit and to store the target instruction code to a page unit in a memory.

7. The processor according to claim 1, comprising

an encryption processing circuit performs encryption of the first program by using the specified an encryption key when the encryption key is specified in authentication information corresponding to the first program.

8. The processor according to claim 7,

wherein, when the encryption key is not specified in the authenticated information, the encryption processing circuit performs encryption of the first program by using an arbitrary page key.

9. The secure processor according to claim 1, comprising

an encryption processing circuit configured to perform encryption of the data of an process corresponding to the authenticated first program by using a different encryption key which is different from the key for the first program.

10. The processor according to claim 1, comprising

a code execution termination processing circuit configured to terminate the execution of the first program for which the authentication by the authentication circuit has failed.

11. The processor according to claim 1, comprising

a normal core monitoring circuit configured to terminate operation of the normal core circuit or branch out to a specific processing when the secure core circuit monitors the operation of the normal core circuit after booting of the normal core circuit and an abnormal state is detected.

12. The processor according to claim 1,

wherein the secure core circuit is configured to supply a core control signal to the normal core circuit to control the operations of the normal core circuit.

13. The processor according to claim 1,

wherein an access to the key is permitted to the secure core circuit, and the access to the key is prohibited to the normal core circuit.

14. The processor according to claim 6, comprising

an illegal instruction execution termination circuit configured to terminate the execution of the encrypted first program at the page unit when an illegal instruction is detected while the encrypted first program stored in the memory is executed.

15. The processor according to claim 1, comprising

an encryption processing circuit configured to perform encryption of the data of an process corresponding to the authenticated first program by using the key corresponding to the first program when the first program is stored in a data storage area.

16. The processor according to claim 13, comprising

a key generation circuit configured to generate a pair of a public key and a secret key, and a shared key, by using the key stored in the key memory circuit under control of the secure core circuit.

17. The processor according to claim 16,

wherein the secure core circuit is configured to inform exteriorly a public key generated by the key generation circuit via the normal core circuit, to receive an original text which is encrypted by using the public key externally via the normal core circuit, and to decrypt the encrypted original text by using the secret key.

18. A processor comprising:

a key memory circuit configured to store a key;

an instruction code memory circuit configured to store a first program in a non-rewritable format;

an authentication circuit configured to authenticate a second program by an execution of the first program by using the key and an electronic signature corresponding to the second program;

a secure core circuit configured to execute the second program which is authenticated by the authentication circuit, the key memory circuit being connected to the secure core circuit; and

a normal core circuit physically separated from the secure core circuit and configured to be booted in response to the execution of the second program by the secure core circuit, the normal core circuit being configured to execute a third program which is not authenticated by the authentication circuit after being booted, the key memory circuit not being connected to the normal core circuit.

19. The processor according to claim 18,

wherein the key is specific to the secure core circuit.

20. The processor according to claim 18,

wherein the instruction code memory circuit is configured to store the first program in an encrypted format.

21. The processor according to claim 18,

wherein the authentication circuit is configured to decrypt the electronic signature by using the key and to authenticate the second program when an obtained decryption result matches a result of an operation performed on the second program.

22. The processor according to claim 18,

wherein the normal core circuit is booted after the secure core circuit is booted.

23. The processor according to claim 18, comprising

an encryption processing circuit configured to encrypt a target instruction code which is included in the second program and authenticated by the authentication circuit and to store the target instruction code to a page unit in a memory.

24. The processor according to claim 18, comprising

an encryption processing circuit performs encryption of the second program by using an encryption key when the encryption key is specified in authentication information corresponding to the second program.

25. The processor according to claim 24,

wherein, when the encryption key is not specified in the authenticated information, the encryption processing circuit performs encryption of the second program by using an arbitrary page key.

26. The secure processor according to claim 18, comprising

an encryption processing circuit configured to perform encryption of the data of an process corresponding to the authenticated second program by using a different encryption key which is different from the key for the second program.

27. The processor according to claim 18, comprising

a code execution termination processing circuit configured to terminate the execution of the second program for which the authentication by the authentication circuit has failed.

28. The processor according to claim 18, comprising

a normal core monitoring circuit configured to terminate operation of the normal core circuit or branch out to a specific processing when the secure core circuit monitors the operation of the normal core circuit after booting of the normal core circuit and an abnormal state is detected.

29. The processor according to claim 18,

wherein the secure core circuit is configured to supply a core control signal to the normal core circuit to control the operations of the normal core circuit.

30. The processor according to claim 18,

wherein an access to the key is permitted to the secure core circuit, and the access to the key is prohibited to the normal core circuit.

31. The processor according to claim 23, comprising

an illegal instruction execution termination circuit configured to terminate the execution of the encrypted second program at the page unit when an illegal instruction is detected while the encrypted second program stored in the memory is executed.

32. The processor according to claim 18, comprising

an encryption processing circuit configured to perform encryption of the data of an process corresponding to the authenticated second program by using the key corresponding to the second program when the second program is stored in a data storage area.

33. The processor according to claim 30, comprising

a key generation circuit configured to generate a pair of a public key and a secret key, and a shared key, by using the key stored in the key memory circuit under control of the secure core circuit.

34. The processor according to claim 33,

wherein the secure core circuit is configured to inform exteriorly a public key generated by the key generation circuit via the normal core circuit, to receive an original text which is encrypted by using the public key externally via the normal core circuit, and to decrypt the encrypted original text by using the secret key.

35. A processor comprising:

a key memory circuit configured to store a key;

an instruction code memory circuit configured to store a first program in a non-rewritable format;

an authentication circuit configured to authenticate the first program by using the key and an electronic signature corresponding to the first program;

a secure core circuit configured to execute the first program which is authenticated by the authentication circuit, the key memory circuit being accessible from the secure core circuit; and

a normal core circuit physically separated from the secure core circuit and configured to be booted in response to the execution of the first program by the secure core circuit, the normal core circuit being configured to execute a second program which is not authenticated by the authentication circuit after being booted, the key memory circuit not being accessible from the normal core circuit.

36. The processor according to claim 35,

wherein the key is specific to the secure core circuit.

37. The processor according to claim 35,

wherein the instruction code memory circuit is configured to store the first program in an encrypted format.

38. The processor according to claim 35,

wherein the authentication circuit is configured to decrypt the electronic signature by using the key and to authenticate the first program when an obtained decryption result matches a result of an operation performed on the first program.

39. The processor according to claim 35, comprising

an encryption processing circuit configured to encrypt a target instruction code which is included in the first program and authenticated by the authentication circuit and to store the target instruction code to a page unit in a memory.

40. The processor according to claim 35, comprising

a code execution termination processing circuit configured to terminate the execution of the first program for which the authentication by the authentication circuit has failed.

41. The processor according to claim 35, comprising

a normal core monitoring circuit configured to terminate operation of the normal core circuit or branch out to a specific processing when the secure core circuit monitors the operation of the normal core circuit after booting of the normal core circuit and an abnormal state is detected.

42. The processor according to claim 35, comprising

an encryption processing circuit configured to perform encryption of the data of an process corresponding to the authenticated first program by using the key corresponding to the first program when the first program is stored in a data storage area.

43. The processor according to claim 35, comprising

a key generation circuit configured to generate a pair of a public key and a secret key, and a shared key, by using the key stored in the key memory circuit under control of the secure core circuit.

44. A processor comprising:

a key memory circuit configured to store a key;

an instruction code memory circuit configured to store a first program in a non-rewritable format;

an authentication circuit configured to authenticate a second program by an execution of the first program by using the key and an electronic signature corresponding to the second program;

a secure core circuit configured to execute the second program which is authenticated by the authentication circuit, the key memory circuit being accessible from the secure core circuit; and

a normal core circuit physically separated from the secure core circuit and configured to be booted in response to the execution of the second program by the secure core circuit, the normal core circuit being configured to execute a third program which is not authenticated by the authentication circuit after being booted, the key memory circuit not being accessible from the normal core circuit.

45. The processor according to claim 44,

wherein the key is specific to the secure core circuit.

46. The processor according to claim 44,

wherein the instruction code memory circuit is configured to store the first program in an encrypted format.

47. The processor according to claim 44,

wherein the authentication circuit is configured to decrypt the electronic signature by using the key and to authenticate the second program when an obtained decryption result matches a result of an operation performed on the second program.

48. The processor according to claim 44, comprising

an encryption processing circuit configured to encrypt a target instruction code which is included in the second program and authenticated by the authentication circuit and to store the target instruction code to a page unit in a memory.

49. The processor according to claim 44, comprising

a code execution termination processing circuit configured to terminate the execution of the second program for which the authentication by the authentication circuit has failed.

50. The processor according to claim 44, comprising

a normal core monitoring circuit configured to terminate operation of the normal core circuit or branch out to a specific processing when the secure core circuit monitors the operation of the normal core circuit after booting of the normal core circuit and an abnormal state is detected.

51. The processor according to claim 44, comprising

an encryption processing circuit configured to perform encryption of the data of an process corresponding to the authenticated second program by using the key corresponding to the second program when the second program is stored in a data storage area.

52. The processor according to claim 44, comprising

a key generation circuit configured to generate a pair of a public key and a secret key, and a shared key, by using the key stored in the key memory circuit under control of the secure core circuit.