Memory device, memory module including the memory device, method of fabricating the memory module, and method of repairing the memory module

• US 9,672,891 B2
• Filed: 02/04/2016
• Issued: 06/06/2017
• Est. Priority Date: 08/27/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Sang-Seok, Kang, Dan-Kyu, Ahn, Young-Man
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US15/015,754
• Publication Number:
  US 20160155487A1
• Time in Patent Office: 488 Days
• Field of Search: 365222, 365 96, 365149, 365186, 365189011, 3651892, 36523003, 36523006, 3652331, 365 3, 365 51
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40607 Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB.

Claims

1. A memory module, comprising:

a PCB; and

a plurality of DRAMs mounted on the PCB,

wherein at least one DRAM has a refresh period different from refresh periods of other DRAMs according to a position where the at least one DRAM is mounted on the PCB.

2. The memory module of claim 1,

wherein the at least one DRAM is configured to set the refresh period based on the position.

3. The memory module of claim 1,

wherein the at least one DRAM comprises:

a data storage unit;

an I/O buffer coupled to the data storage unit; and

a latency controller configured to adjust latency of the I/O buffer based on the position.

4. The memory module of claim 1,

wherein the at least one DRAM comprises:

a data storage unit;

a DC generator configured to supply an internal voltage to the data storage unit; and

a DC controller configured to control the DC generator based on the position,

wherein the internal voltage includes at least one of a bit line voltage, a body bias voltage, and a cell plate voltage.

5. The memory module of claim 2,

wherein the at least one DRAM comprises:

a data storage unit;

a refresh controller configured to refresh the data storage unit; and

a refresh period controller configured to adjust a refresh period of the data storage unit based on the position.

6. A memory module, comprising:

a register disposed at a center region;

a first DRAM disposed at a first distance from the register, wherein the first DRAM has a first operating parameter; and

a second DRAM disposed at a second distance from the register, wherein the second DRAM has a second operating parameter,

wherein the first operating parameter is different from the second operating parameter,

wherein the first operating parameter includes a first refresh period and the second operating parameter includes a second refresh period,

wherein the first DRAM is configured to set the first refresh period based on the first distance, and

wherein the second DRAM is configured to set the second refresh period based on the second distance.

7. The memory module of claim 6,

wherein each of the first operating parameter and the second operating parameter includes at least one of an alternating current (AC) parameter and a direct current (DC) parameter,

wherein the first DRAM is configured to set the first operating parameter based on the first distance, and

wherein the second DRAM is configured to set the second operating parameter based on the second distance.

8. The memory module of claim 6,

wherein the first DRAM comprises:

a data storage unit;

a refresh controller configured to refresh the data storage unit;

a fuse block configured to store a refresh period setting value; and

a refresh period controller configured to control the refresh controller based on the refresh period setting value, and adjust a refresh period of the data storage unit.

9. The memory module of claim 8,

wherein the fuse block includes at least one of an electrical fuse, an anti-fuse, and a laser fuse.

10. The memory module of claim 7,

wherein the first DRAM comprises:

a data storage unit;

a DC generator configured to supply internal voltage to the data storage unit;

a fuse block configured to store a DC setting value; and

a DC controller configured to control the DC generator to adjust the internal voltage based on the DC setting value.